CDB8952T-IQ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CDB8952T-IQ Datasheet PDF : 86 Pages
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CS8952T
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
internal oscillator, using an external oscillator sup-
plied through the XTAL_I pin, or using an external
clock source supplied through the TX_CLK pin.
When a 25 MHz crystal is used, it should be placed
within one inch of the XTAL_I and XTAL_O pins
of the CS8952T. The crystal traces should be short,
have no vias, and run on the component side.
Table 10 lists examples of manufacturers of suit-
able crystals. The designer should evaluate their
crystal selection for suitability in their specific de-
sign.
Alternately, an external CMOS clock source may
be connected to the XTAL_I pin, with XTAL_O
left open. The input capacitance of the XTAL_I pin
is larger than the other inputs (a maximum of
35pF), since it includes the additional load capaci-
tance of the crystal oscillator. Care should be taken
to assure any external clock source attached to
XTAL_I is capable of driving higher capacitive
loads. The clock signal should be 25 MHz ±0.01%
with a duty cycle between 45% and 55%.
The third alternative is to supply a TTL-level clock
to both a MAC and the CS8952T’s TX_CLK pin.
In this case the XTAL_I pin should be left uncon-
nected, and the TCM pin should be left unconnect-
ed or pulled high. The clock skew between the
TX_CLK input and the TXD[4:0] pins is tightly
controlled, assuring data is latched correctly.
Recommended Magnetics
The CS8952T requires an isolation transformer
with a 1:1 turns ratio for both the transmit and re-
ceive signals. Table 10 lists examples of manufac-
turers with transformers meeting these
requirements. However, the designer should evalu-
ate the magnetics for suitability in their specific de-
sign.
Power Supply and Decoupling
The CS8952T supports connection to either a 3.3 V
or 5.0 V MII. When connected to a +5.0 V MII, all
power pins should be provided +5.0 V +/- 5%, and
all digital signal inputs should be referenced to
+5.0V. When interfaced with a 3.3 V MII,
VDD_MII power pins should be provided +3.3 V
+/- 5%, VDD power pins should be provided
+5.0 V +/- 5%, and all signal inputs, with the ex-
ception of XTAL_I, should be referenced to
+3.3 V.
Component Manufacturer
Part Number
Crystal
Raltron Electronics Corp.
10651 NW 19th St.
Miami, FL 33172
(305) 593-6033
www.raltron.com
AS-25.000-15-F-
EXT-SMD-TR-
CIR
Transformer Halo Electronics, Inc.
P.O. Box 5826
TG22-3506ND
Redwood City, CA 94063
USA
(650) 568-5800
www.haloelectronics.com
Bel Fuse, Inc.
198 Van Vorst Street
S5558-5999-46
Jersey City, NJ 07302 USA
(201) 432-0463
www.belfuse.com
Pulse Engineering
PE-68515
12220 World Trade Drive
San Diego, CA 92128 USA
(619) 674-8100
www.pulseeng.com
Table 10. Support Component Manufacturers
Each CS8952T power pin should be connected to a
0.1 µF bypass capacitor and then to the power
plane. The bypass capacitors should be located as
close to its corresponding power pin as possible.
Connect ground pins directly to the ground plane.
General Layout Recommendations
The following PCB layout recommendations will
help ensure reliable operation of the CS8952T and
good EMC performance.
• Use a multilayer Printed Circuit Board with at
least one ground and one power plane. A typi-
cal +5V MII application would be as follows:
Layer 1: (top) Components and first choice sig-
nal routing
Layer 2: Ground
Layer 3: Power (+5V)
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
64
DS206TPP2
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