When the JTAG tests are applied by ATE, care must be taken to disable any other devices
driving the digital I/O pins. If the tests are to be applied only at ATE, this can be
accomplished with tri-state buffers used in conjunction with the JTAG/HOST input
signal. This is shown in Figure 4-31.
Application HOST
GS1582
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
JTAG_HOST
In-circuit ATE probe
Figure 4-31: In-Circuit JTAG
Alternatively, if the test capabilities are to be used in the system, the host processor may
still control the JTAG/HOST input signal, but some means for tri-stating the host must
exist in order to use the interface at ATE. This is represented in Figure 4-32.
Application HOST
GS1582
CS_TMS
SCLK_TCK
SDIN_TDI
Tri-State
In-circuit ATE probe
Figure 4-32: System JTAG
SDOUT_TDO
JTAG_HOST
NOTE: Scan coverage is limited to digital pins only. There is no scan coverage for analog
pins VCO, SDO/SDO, RSET, LF, and CP_RES.
NOTE: The SD/HD pin must be held LOW during scan and therefore has no scan
coverage.
Please contact your Gennum representative to obtain the BSDL model for the GS1582.
GS1582 Multi-Rate Serializer with Cable Driver, Audio
Multiplexer and ClockCleanerTM
Data Sheet
40117 - 4
December 2011
107 of 115