GS1582-IBE3 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
Manufacturer
GS1582-IBE3
Semtech Corporation
GS1582-IBE3 Datasheet PDF : 115 Pages
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5. Application Reference Design
5.1 Typical Application Circuit (Part A)
VCO_GND
2.5V INTERNAL ISOLATED POWER
PLACE AS CLOSE AS
POSSIBLE TO THE PINS
OF THE GS1582.
CONNECT DIRECTLY
TO PINS OF GS1582.
CONTROL SIGNALS
5
6
VCO_VCC 7
VCO_GND
VCTR
GND
VCC
NC 3
GND 2
O/P 1
VCO_GND
10n
GO1555
VCO_GND
VCO_VCC
33uF
3R3
*R & C:
R*
Refer to Section 4.11.2 for
Loop Filter Component Values.
VCO_GND
+3.3V
10n
+1.8V_A +3.3V_CD
10n
GND_A
10n
GND_A
+1.8V
IO_VDD
1
2
1u
0R
0R
1u
1
2
10n
VCO_GND
RESETn
SMPTE_BY PASSn
DVB_ASI
SD/HDn
JTAG/HOSTn
BLANKn
IOPROC_EN/DISn
20bit/10bitn
SDO_EN/DISn
DETECT_TRS
STANDBY
TIMING_SEL
RESET
SMPTE_BY PASS
DVB-ASI
SD/HD
JTAG/HOST
BLANK
IOPROC_EN/DIS
20bit/10bit
SDO_EN/DIS
DETECT_TRS
STANDBY
TIMING_SELECT
C*
VCO_GND
PARALLEL DATA INPUT[19:0]
PCLK INPUT (f rom GS4911B)
FVH INPUT[2:0] (f rom GS4911B)
10KR
VCO_GND
A9
A8
B9
B8
B7
A7
VCO
VCO_VCC
VCO_GND
VCO_GND
CP_RES
LF
DATA_IN19
DATA_IN18
DATA_IN17
DATA_IN16
DATA_IN15
DATA_IN14
DATA_IN13
DATA_IN12
DATA_IN11
DATA_IN10
DATA_IN9
DATA_IN8
DATA_IN7
DATA_IN6
DATA_IN5
DATA_IN4
DATA_IN3
DATA_IN2
DATA_IN1
DATA_IN0
B3
A2
A1
B2
B1
C2
C1
C3
D1
D2
F1
F2
H1
H2
J1
J2
K1
K2
J3
K3
DIN19
DIN18
DIN17
DIN16
DIN15
DIN14
DIN13
DIN12
DIN11
DIN10
DIN9
DIN8
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
PCLK_1582
B4 PCLK
F/DE_GS4911B
A3
V/VSY NC_GS4911B C4
H/HSY NC_GS4911B A4
F/DE
V/VSY NC
H/HSY NC
A_INT
H7 AUDIO_INT
NP
NP
EN_GRP1
ACLK_1
WCLK_1
AIN1_2
AIN3_4
H6
K7
J7
J6
K6
GRP1_EN/DIS
ACLK_1
WCLK_1
AIN_1/2
AIN_3/4
EN_GRP2
ACLK_2
WCLK_2
AIN5_6
AIN7_8
H5
K5
J5
J4
K4
GRP2_EN/DIS
ACLK_2
WCLK_2
AIN_5/6
AIN_7/8
RESET
SMPTE_BY PASS
SD/HD
DVB_ASI
JTAG/HOST
BLANK
IOPROC_EN/DIS
20BIT/10BIT
SDO_EN/DIS
DETECT_TRS
STANDBY
TIM_861
G8
G6
E3
G5
H8
H3
G7
G4
D4
F3
D3
G3
LOCKED H4
RESETn
SMPTE_BY PASSn
SD/HDn
DVB_ASI
JTAG/HOSTn
ANC_BLANKn
IOPROC_EN/DISn
20bit/10bitn
SDO_EN/DISn
DETECT_TRS
STANDBY
TIMING_SEL
LOCKED
GS1582
NC
NC
NC
NC
NC
RSV
NC
D6
D7
D8
E4
E8
F4
F8
RSET F10
SDO
SDO
C10
D10
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
K9
J10
K10
J9
+3.3V_CD
R and L form the Output Return
Loss compensation Network.
SUBJECT TO CHANGE
5n6
4u7
750R +/- 1%
75R
75R
+3.3V_CD
+3.3V
22k
CSn
SCLK
SDIN
SDOUT
75R
75R
5n6
10n
4u7
BNC
GND_A
GND_A
BNC
GND_A
GSPI[3:0]
GND_A
AUDIO SIGNALS
A_INT
EN_GRP1
ACLK_1
WCLK_1
AIN1_2
AIN3_4
EN_GRP2
ACLK_2
WCLK_2
AIN5_6
AIN7_8
AUDIO INTERRUPT
PRIMARY AUDIO GROUP ENABLE
PRIMARY GROUP AUDIO CLOCK
PRIMARY GROUP WORD CLOCK
AUDIO CHANNELS 1 & 2
AUDIO CHANNELS 3 & 4
SECONDARY AUDIO GROUP ENABLE
SECONDARY GROUP AUDIO CLOCK
SECONDARY GROUP WORD CLOCK
AUDIO CHANNELS 5 & 6
AUDIO CHANNELS 7 & 8
(ACLK and WCLK may be supplied by
GS4911B audio clock outputs.)
ANALOG POWER FILTERING
+3.3V
+3.3V_CD
0R
10n
1u
1u
10n
GND_A
+1.8V
10n
0R
1u
1u
0R
+1.8V_A
10n
GND_A
GS1582 Multi-Rate Serializer with Cable Driver, Audio
Multiplexer and ClockCleanerTM
Data Sheet
40117 - 4
December 2011
109 of 115
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