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GS1582-IBE3 View Datasheet(PDF) - Semtech Corporation

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GS1582-IBE3 Datasheet PDF : 115 Pages
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4.3.2 CEA 861 Timing
The GS1582 extracts timing information from externally provided HSYNC, VSYNC, and
DE signals when CEA 861 timing mode is selected by setting DETECT_TRS = LOW and
the TIM_861 = HIGH.
Horizontal sync (H), Vertical sync (V), and Data Enable (DE) timing must be provided via
the H/HSYNC, V/VSYNC and F/DE input pins. The host interface register bit H_CONFIG
will be ignored in the CEA 861 input timing mode.
The GS1582 will determine the EIA/CEA-861 standard and embed EAV and SAV TRS
words in the output serial video stream.
Video standard detection is not dependent on the HSYNC pulse width or the VSYNC
pulse width and therefore the GS1582 will tolerate non-standard pulse widths. In
addition, the device can compensate for up to ±1 PCLK cycle of jitter on VSYNC with
respect to HSYNC and sample VSYNC correctly.
NOTE 1: The period between the leading edge of the HSYNC pulse and the leading edge
of Data Enable (DE) must follow the timing requirements described in the EIA/CEA-861
specification. The GS1582 embeds TRS words according to this timing relationship to
maintain compatibility with the corresponding SMPTE standard.
NOTE 2: When CEA 861 standards 6 & 7 [720(1440)x480i] are presented to the GS1582,
the device will embed TRS words corresponding to the timing defined in SMPTE 125M
to maintain SMPTE compatibility.
CEA 861 standards 6 & 7 [720(1440)x480i] define the active area on lines 22 to 261 and
285 to 524 inclusive (240 active lines per field). SMPTE 125M defines the active area on
lines 20 to 263 and 283 to 525 inclusive (244 lines on field 1; 243 lines on field 2).
Therefore, in the first field, the GS1582 adds two active lines above and two active lines
below the original active image. In the second field it adds two lines above and one line
below the original active image.
GS1582 Multi-Rate Serializer with Cable Driver, Audio
Multiplexer and ClockCleanerTM
Data Sheet
40117 - 4
December 2011
31 of 115

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