GS1582-IBE3 View Datasheet(PDF) - Semtech Corporation

Part Name

Description

Manufacturer

GS1582-IBE3

Multi-Rate Serializer with Cable Driver, Audio Multiplexer and ClockCleaner™

Semtech Corporation 

PCLK. The recovery time from standby mode is the same as initial power-up but no reset

is required. Once the GS1582 re-locks to the reference PCLK, operation is resumed

according to the configuration held before entering standby mode.

Table 4-2: Standby Power Consumption

Standby Condition

STANDBY asserted

STANDBY asserted

Parallel data and clock inactive

STANDBY asserted

3.3V supply removed from CD_VDD

STANDBY asserted

Parallel data and clock inactive

3.3V supply removed from CD_VDD

Typical Power Consumption (mW)

125

100

35

<10

4.7 Audio Multiplexer

Up to eight channels of audio may be embedded into the GS1582 video data stream in

accordance with SMPTE 299M and SMPTE 272M. The audio data is input in two groups

of four channels, with corresponding clock signals.

The audio input signal formats supported include AES/EBU and three other industry

standard serial digital formats. 16, 20 and 24-bit audio sample sizes are supported at

48kHz synchronous for SD formats and 48kHz synchronous or asynchronous for HD

formats.

Additional audio processing features include audio mute, individual channel enable,

channel re-mapping, audio group replacement, cascade, group selection, and audio

channel status insertion.

The audio system clock can be provided by Gennum’s GEN-ClocksTM series of clock

generation ICs. In serial formats, the audio clocks required by the core are two word

clocks and two signals that are a multiple of 64fs.

The SD audio multiplexer core is compliant with SMPTE 272M A and C. The HD audio

multiplexer core is fully compliant with SMTPE 299M.

4.7.1 Audio Core Configurations

Figure 4-10 shows the top level block diagrams of both the SD and HD multiplexer cores.

Each group of audio has one word clock signal and one audio clock signal. Data present

at Ain_1/2 and Ain_3/4 share clocks present at WCLK1 and ACLK1, while data present

at Ain_5/6 and Ain_7/8 share clocks present at WCLK2 and ACLK2.

Audio embedding may be disabled for each group independently using the pins

GRP1_EN/DIS and GRP2_EN/DIS.

GS1582 Multi-Rate Serializer with Cable Driver, Audio

Multiplexer and ClockCleanerTM

Data Sheet

40117 - 4

December 2011

37 of 115

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