GS1582-IBE3 View Datasheet(PDF) - Semtech Corporation

Part Name

Description

Manufacturer

GS1582-IBE3

Multi-Rate Serializer with Cable Driver, Audio Multiplexer and ClockCleaner™

Semtech Corporation 

4.7.12 Channel and Group Activation

Multiplexing of individual audio channels is enabled by setting the ACT bits in host

interface register 0Ch. When set HIGH, the corresponding audio channel is multiplexed

into the video data stream. Channels designated as not active (ACT set LOW) will be

embedded with null samples (all bits set to zero). When all ACT bits are set LOW, no

audio data packets will be multiplexed.

When ACT[1-4] are set LOW, the audio group set in IDA[1:0] will not be multiplexed.

Similarly, when ACT[5-8] are set LOW, the audio group set in IDB[1:0] will not be

multiplexed. This allows four channel, single group operation.

By default, all audio channels are enabled.

Refer to Section 4.13.3 for HD and SD audio multiplexer status and configuration

registers.

4.7.13 ECC Error Detection & Correction (HD Mode Only)

The GS1582 will generate the error detection and correction fields in the audio data

packets.

All generated error detection and correction complies with SMPTE 299M.

4.7.14 Interrupt Control

The GS1582 can be programmed to assert the interrupt signal (AUDIO_INT, pin H7)

whenever an internal interrupt condition exists.

To enable a particular type of interrupt, the corresponding bit in the host interface must

be set. If the audio interrupt bit is un-masked, and the interrupt condition is met, the

AUDIO_INT pin will go HIGH. For example, if the EN_ADPG_1 is enabled, and the

incoming video has embedded audio in group one, then the AUDIO_INT pin will go

HIGH.

Please refer to Section 4.13.3 for HD and SD audio multiplexer status and configuration

registers for a complete listing of the audio interrupts.

4.7.15 Audio Clocks

The audio multiplexer has 4 clock inputs: ACLK_1, ACLK_2, WCLK_1 and WCLK_2. For

serial audio input modes ACLK_1/2 must be provided at 64fs, where fs is the

fundamental sampling frequency of 48kHz. An audio word clock at 48kHz must also be

supplied at the WCLK_1/2 inputs. For AES/EBU audio input mode, the ACLK_1/2 and

WLCK_1/2 inputs are not required. All required clocks will automatically be derived

from the AES/EBU preambles. ACLK_1/2 and WCLK_1/2 will be HIGH impedance in

AES/EBU audio input mode.

GS1582 Multi-Rate Serializer with Cable Driver, Audio

Multiplexer and ClockCleanerTM

Data Sheet

40117 - 4

December 2011

51 of 115

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