QL82SD Device Data Sheet Rev C
Input (d)
clk
tSU
tH
Figure 30: Setup and Hold Time for Flip-Flop
Figure 31: Delay from Clock Input to Flip-Flop Q Output
Figure 32: Clock High and Low Time for Flip-Flop
Figure 33: Timing Requirements for Flip-Flop SET and RESET
© 2002 QuickLogic Corporation
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