QL82SD-5PS484C View Datasheet(PDF) - QuickLogic Corporation
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QL82SD-5PS484C Datasheet PDF : 60 Pages
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QL82SD Device Data Sheet Rev C
Table 26: Output Register Cell
Symbol
Parameter
Output Register Cell Only
tOUTLH
tOUTHL
tPZH
tPZL
tPHZ
tPLZ
tCO
Output Delay low to high (10% of H)
Output Delay high to low (90% of H)
Output Delay tri-state to high (10% of Z)
Output Delay tri-state to low (90% of Z)
Output Delay high to tri-State
Output Delay low to tri-State
Clock to out delay
Propagation delay (ns)
0.40
0.55
2.94
2.34
3.07
2.53
3.15 (fast slew) 10.2(slow slew)
tOUTHL
H
H
L
L
tOUTLH
H
H
Z
tPZH
Z
L
L
H
H
Z
Z
L
L
tPLZ
tPZL
tPHZ
Figure 39: Output Register Cell Timing
Electrical Specification - RAM Block
[9:0]
[17:0]
[1:0]
WA
WD
WE
WCL K
MOD E
RE
RCLK
[9:0]
RA
[17:0]
RD
ASYNCRD
Figure 40: RAM Module
© 2002 QuickLogic Corporation
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