SMC032BF View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
SMC032BF Datasheet PDF : 91 Pages
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Command Interface
SMCxxxBF
Figure 9. True IDE Multi-Word DMA Mode Read/Write waveforms
tM
t0
tN
−CS0, −CS1
tLW, tLR
−∆ΜΑΡΘ
tI
tD
tKW
tKR
tJ
−∆ΜΑΧΚ
tE
−IORD/−IOWR
Read Data D0-D15
Write Data D0-D15
tF
VALID
tG
tH
VALID
tZ
VALID
VALID
ai13117
Table 23. True IDE Multi-Word DMA Mode Read/Write timing
Symbol
Parameter
Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Unit
t0(1)
Cycle time (min)
tD(1)
-IORD / -IOWR asserted width (min)
480
150
120
100
215
80
70
65
80 ns
55 ns
tE
-IORD data access (max)
150
60
50
50
45 ns
tF
-IORD data hold (min)
5
5
5
5
5 ns
tG
-IORD/-IOWR data setup (min)
100
30
20
15
10 ns
tH
-IOWR data hold (min)
20
15
10
5
5 ns
tI
DMACK to –IORD/-IOWR setup (min)
0
0
0
0
0 ns
tJ
-IORD / -IOWR to -DMACK hold (min)
20
5
5
5
5 ns
tKR(1)
-IORD Low width (min)
50
50
25
25
20 ns
tKW(1)
-IOWR Low width (min)
215
50
25
25
20 ns
tLR
-IORD to DMARQ delay (max)
120
40
35
35
35 ns
tLW
-IOWR to DMARQ delay (max)
40
40
35
35
35 ns
tM
CS(1:0) valid to –IORD / -IOWR
50
30
25
10
5 ns
tN
CS(1:0) hold
15
10
10
10
10 ns
tZ
-DMACK
20
25
25
25
25 ns
1. t0 is the minimum total cycle time. tD is the minimum command active time. tKR and tKW are the minimum command
recovery time or command inactive time for input and output cycles, respectively. The actual cycle time is the sum of the
actual command active time and the actual command inactive time. The timing requirements of t0, tD, tKR, and tKW must be
respected. t0 is higher than tD + tKR or tD + tKW, for input and output cycles respectively. This means the host can lengthen
either tD or tKR/tKW, or both, to ensure that t0 is equal to or higher than the value reported in the device’s identify device
data. A CompactFlash Storage Card implementation shall support any legal host implementation.
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