MSP3400CPP View Datasheet(PDF) - Micronas

Part Name

Description

Manufacturer

MSP3400CPP

Multistandard Sound Processor

Micronas 

PRELIMINARY DATA SHEET

MSP 3400C

7.3. Summary of Readable Registers

All readable registers are 16 bit wide. Transmissions via

I2C bus have to take place in 16 bit words. Single data

entries are 8 bit. Some of the defined 16 bit words are

divided into low and high byte, thus holding two different

control entities.

These registers are not writeable.

Name

Stereo detection register

Quasi peak readout left

Quasi peak readout right

DC level readout FM1/Ch2–L

DC level readout FM2/Ch1–R

MSP hardware version code

MSP major revision code

MSP product code

MSP ROM version code

Address

0018hex

0019hex

001ahex

001bhex

001chex

001ehex

001fhex

High/Low

H

H&L

H&L

H&L

H&L

H

L

H

L

Output Range

[80hex ... 7Fhex]

[00hex ... 7FFFhex]

[00hex ... 7FFFhex]

[00hex ... 7FFFhex]

[00hex ... 7FFFhex]

[00hex ... FFhex]

[00hex ... FFhex]

[00hex ... 0Ahex]

[00hex ... FFhex]

8 bit two’s complement

16 bit binary

16 bit binary

16 bit binary

16 bit binary

7.3.1. Stereo Detection Register

Stereo Detection

Register

Stereo Mode

MONO

STEREO

BILINGUAL

0018hex

H

Reading

(two’s complement)

near zero

positive value (ideal

reception: 7Fhex)

negative value (ideal

reception: 80hex)

7.3.2. Quasi Peak Detector

Quasi peak readout

left

Quasi peak readout

right

Quasi peak readout

0019hex

H+L

001ahex

H+L

[0hex ... 7FFFhex]

values are 16 bit binary

The quasi peak readout register can be used to read out

the quasi peak level of any input source, in order to ad-

just all inputs to the same normalized listening level. The

refresh rate is 32 kHz. The feature is based on a filter

time constant:

attack-time: 1.3 ms

decay-time: 37 ms

Micronas

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