PRELIMINARY DATA SHEET
8.4. Pin Circuits
DVSUP
P
N
GND
Fig. 8–9: Output Pins 1, 5, 13, 14, and 68
(S_ID, I2S_DA_OUT, D_CTR_OUT0/1, S_CL)
DVSUP
P
N
GND
Fig. 8–10: Input Pins 4 and 65
(I2S_DA_IN1/2)
N
GND
Fig. 8–11: Input/Output Pins 8 and 9
(I2C_DA, I2C_CL)
Fig. 8–12: Input Pins 11, 12, 61, and 62
(STANDBYQ, ADR_SEL, RESETQ, TESTEN)
DVSUP
P
N
GND
Fig. 8–13: Input/Output Pins 6 and 7
(I2S_WS, I2S_CL)
Micronas
MSP 3400C
2.5 V
Fig. 8–14: Input Pin 19 (DMA_SYNC)
DVSUP
P
N
GND
Fig. 8–15: Input Pin 3
(S_DA_IN)
P
3–30 pF
500 k
N
2.5 V
3–30 pF
Fig. 8–16: Output/Input Pins 18, 20, and 21
(AUD_CL_OUT, XTALIN/OUT)
ANAIN1+
ANAIN2+
A
D
ANAIN–
VREFTOP
Fig. 8–17: Input Pins 23–25 and 29
(ANA_IN2+, ANA_IN–, ANA_IN1+, VREFTOP)
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