MSP 3400C
PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name
Min. Typ. Max. Unit
Load Capacitance Recommendations for Master-Slave Applications
CL
External Load Capacitance2)
XTAL_IN,
PSDIP
1.5
XTAL_OUT
PLCC
3.3
fCL
Required Open Loop Clock
Frequency (Tamb = 25°C)
18.431
18.433
Crystal Recommendations for FM Application (No Master-Slave Mode possible)
fP
Parallel Resonance Frequency at
12 pF Load Capacitance
18.432
fTOL
DTEM
Accuracy of Adjustment
Frequency Variation versus
Temperature
–100
–50
+100
+50
RR
Series Resistance
C0
Shunt (Parallel) Capacitance
8
25
6.2
7.0
Load Capacitance Recommendations for FM Application (No Master-Slave Mode possible)
CL
External Load Capacitance2)
XTAL_IN,
PSDIP
1.5
XTAL_OUT
PLCC
3.3
pF
pF
MHz
MHz
ppm
ppm
Ω
pF
pF
pF
Amplitude Recommendation for Operation with External Clock Input (Cload after reset = 22 pF)
VXCA
External Clock Amplitude
XTAL_IN
0.7
Vpp
Analog Input and Output Recommendations
CAGNDC
AGNDC-Filter-Capacitor
AGNDC
–20% 3.3
µF
Ceramic Capacitor in Parallel
–20% 100
nF
CinSC
DC-Decoupling Capacitor in front SCn_IN_s1)
of SCART Inputs
–20% 330
+20% nF
VinSC
VinMONO
RLSC
CLSC
CVMA
SCART Input Level
Input Level, Mono Input
SCART Load Resistance
SCART Load Capacitance
Main/AUX Volume Capacitor
MONO_IN
SCn_OUT_s1)
10
CAPL_M,
10
CAPL_A
2.0
VRMS
2.0
VRMS
kΩ
6.0
nF
µF
CFMA
Main/AUX Filter Capacitor
DACM_s,
DACA_s1)
–10% 1
+10% nF
1) “n” means “1”, “2” or “3”, “s” means “L” or “R”, “p” means “M” or “A”
2) External capacitors at each crystal pin to ground are required. They are necessary to tune the open-loop fre-
quency of the internal PLL and to stabilize the frequency in closed-loop operation. The higher the capacitors,
the lower the clock frequency results. The nominal free running frequency should match 18.432 MHz as closely
as possible. Due to different layouts of customer PCBs, the matching capacitor size should be defined in the
application. The suggested values (1.5 pF/3.3 pF) are figures based on experience with various PCB layouts.
56
Micronas