STA309A13TR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STA309A13TR Datasheet PDF : 67 Pages
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Registers
STA309A
7.2.5
Table 24. CSZ definition
CSZ[4:0]
Compensating pulse size
00000
00001
…
11111
0 clock period compensating pulse size
1 clock period compensating pulse size
…
31 clock period compensating pulse size
Table 25. MPC bit
Bit RW RST
Name
7
RW
1
MPC
Description
Max power correction:
1: enable STA50x correction for THD reduction near
maximum power output.
Setting the MPC bit turns on special processing that corrects the STA50x power device at
high power. This mode should lower the THD+N of a full STA50x DDX system at maximum
power output and slightly below. This mode will only be operational in OM[1,0] = 01.
Configuration register E (0x04)
D7
C8BO
0
D6
C7BO
0
D5
C6BO
0
D4
C5BO
0
D3
C4BO
0
D2
C3BO
0
D1
C2BO
0
D0
C1BO
0
Table 26. CnBO bits
Bit RW RST
Name
Description
0
RW
0
C1BO
1
RW
0
C2BO
2
RW
0
C3BO
3
RW
0
C4BO
4
RW
0
C5BO
5
RW
0
C6BO
6
RW
0
C7BO
7
RW
0
C8BO
Channels 1, 2, 3, 4, 5, 6, 7, and 8 binary output
mode enable bits:
0: ordinary DDX tristate output
1: binary output mode.
Each individual channel output can be set to output a binary PWM stream. In this mode
output A of a channel will be considered the positive output and output B is negative inverse.
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Doc ID 13855 Rev 4
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