Z8018X View Datasheet(PDF) - Zilog

Part Name

Description

Manufacturer

Z8018X

Family MPU

Zilog 

Z 8018x Fam ily

M PU Us e r M anual

288

Table 55. Pin Outputs in Each Operating Mode (Continued)

Mode

Internal

DMA

RESET

Address Data

M1 MREQ IORQ RD WR RFSH HALT BUSACK ST BUS BUS

Memory Read 1

0

Memory Write 1

0

I/O Read

1

1

I/O Write

1

1

1

1

1 01 1

*

1 10 1

*

0 01 1

*

0 10 1

*

1 11 1

1

1

0

A

IN

1

0

A OUT

1

0

A

IN

1

0

A OUT

1

1

Z

IN

• 1 : High

• 0 : Low

• A : Programmable

• Z : High Impedance

• IN : Input

• OUT : Output

• * : Invalid

PIN STATUS

Tables 56 describes the status of each ping during RESET and LOW

POWER OPERATION modes.

UM005001-ZMP0400

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