Z8018X View Datasheet(PDF) - Zilog

Part Name

Description

Manufacturer

Z8018X

Family MPU

Zilog 

Z8018x Family

MPU User Manual

300

Table 57. Internal I/O Registers (Continued)

Register

Mnemonics Address

Remarks

MMU Common Base

Register:

CBR

MMU Bank Base Register BBR

MMU Common/Bank

Register

CBAR

38

bit

CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0

during RESET

0

0

0

0

0

0

0

0

R/W

R/W R/W R/W R/W R/W R/W R/W R/W

MMU Common Base Register

39

bit

BB7 BB6 BB5 BB4 BB3 BB2 BB1 BB0

during RESET

0

0

0

0

0

0

0

0

R/W

R/W R/W R/W R/W R/W R/W R/W R/W

MMU Bank Base Register

3A

bit

CA3 CA2 CA1 CA0 BA3 BA2 BA1 BA0

during RESET

1

1

1

1

0

0

0

0

R/W

R/W

R/W R/W R/W R/W R/W R/W R/W

MMU Common Area Register

MMU Bank

Area Register

Operation Mode Control OMCR

Register

I/O Control Register:

ICR

3E

bit

MIE MITE IOC

—

—

—

—

—

during RESET

1

1

1

1

1

1

1

1

R/W

R/W

W

R/W

I/O Compatibility

M1 Temporary Enable

M1 Enable

3F

bit

IOA7 IOA6 IOSTP —

—

—

—

—

during RESET

0

0

0

1

1

1

1

1

R/W

R/W R/W R/W

I/O Stop

I/O Address

UM005001-ZMP0400

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