Description
ST72361xx-Auto
Table 3.
Pin n°
Device pin description (continued)
Pin name
Level
Port
Input(1)
Main
Output function
(after
reset)
Alternate function
44 - - PF0
45 30 - PF1 / AIN7
46 31 - PF2 / AIN8
47 32 23 PD1 / SCI1_RDI
I/O TT
I/O TT
I/O TT
I/O CT
XX
XX
Port F0
XX
X X X Port F1 ADC analog input 7
XX
X X X Port F2 ADC analog input 8
X
ei3
X
X
Port D1
LINSCI1 receive data
input
48 33 24 PD2 / SCI1_TDO
I/O CT
XX
X
X
Port D2
LINSCI1 transmit data
output
49 - - PF3 / AIN9
50 - - PF4
51 - - TLI
52 34 - PF5
I/O TT
I/O TT
I CT
I/O TT
XX
XX
X
X
XX
53 35 25 PD3 (HS) / SCI2_SCK I/O CT HS X X
XX
X
X
X
X Port F3 ADC analog input 9
X
Port F4
Top level interrupt input pin
X
Port F5
X
Port D3
LINSCI2 serial clock
output
54 36 26 PD4 / SCI2_RDI
I/O CT
X
ei3
X
X
Port D4
LINSCI2 receive data
input
55 37 27 VSSA
56 38 28 VSS_0
57 39 29 VDDA
58 40 30 VDD_0
59 41 31 PD5 / SCI2_TDO
S
S
I
S
I/O CT
XX
Analog ground voltage
Digital ground voltage
Analog reference voltage for ADC
Digital main supply voltage
X
X
Port D5
LINSCI2 transmit data
output
60 42 32 RESET
I/O CT
Top priority non maskable
interrupt.
61 43 - PD6 / AIN10
I/O CT
X ei3 X X X Port D6 ADC analog input 10
62 44 - PD7 / AIN11
I/O CT
X
ei3 X X X Port D7 ADC analog input 11
63 - - PF6
I/O TT
XX
XX
Port F6
64 - - PF7
I/O TT
XX
XX
Port F7
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column (wpu) is
merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating
interrupt input.
2. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Chapter 1: Description and
Section 20.5: Clock and timing characteristics for more details.
3. Input mode can be used for general purpose I/O, output mode cannot be used.
On the chip, each I/O port has eight pads. Pads that are not bonded to external pins are in input pull-up configuration after
reset. The configuration of these pads must be kept at reset state to avoid added current consumption.
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Doc ID 12468 Rev 3