ST72361J4-AUTO View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST72361J4-AUTO
STMicroelectronics
ST72361J4-AUTO Datasheet PDF : 279 Pages
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Register and memory map
ST72361xx-Auto
Table 4. Hardware register map (continued)
Address
Block
Register
label
Register name
000Fh
0010h
0011h
0012h
to
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
Port F
PFDR
PFDDR
PFOR
Port F Data Register
Port F Data Direction Register
Port F Option Register
Reserved Area (15 bytes)
SPI
FLASH
ITC
AWU
CKCTRL
WWDG
PWM
ART
8-BIT
TIMER
ADC
SPIDR
SPICR
SPICSR
SPI Data I/O Register
SPI Control Register
SPI Control/Status Register
FCSR
Flash Control/Status Register
ISPR0
ISPR1
ISPR2
ISPR3
EICR0
EICR1
Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3
External Interrupt Control Register 0
External Interrupt Control Register 1
AWUCSR Auto Wake up f. Halt Control/Status Register
AWUPR
Auto Wake Up From Halt Prescaler
SICSR
MCCSR
System Integrity Control / Status Register
Main Clock Control / Status Register
WDGCR
WDGWR
Watchdog Control Register
Watchdog Window Register
PWMDCR3
PWMDCR2
PWMDCR1
PWMDCR0
PWMCR
ARTCSR
ARTCAR
ARTARR
ARTICCSR
ARTICR1
ARTICR2
Pulse Width Modulator Duty Cycle Register
3
PWM Duty Cycle Register 2
PWM Duty Cycle Register 1
PWM Duty Cycle Register 0
PWM Control register
Auto-Reload Timer Control/Status Register
Auto-Reload Timer Counter Access Register
Auto-Reload Timer Auto-Reload Register
ART Input Capture Control/Status Register
ART Input Capture Register 1
ART Input Capture register 2
T8CR2
T8CR1
T8CSR
T8IC1R
T8OC1R
T8CTR
T8ACTR
T8IC2R
T8OC2R
Timer Control Register 2
Timer Control Register 1
Timer Control/Status Register
Timer Input Capture 1 Register
Timer Output Compare 1 Register
Timer Counter Register
Timer Alternate Counter Register
Timer Input Capture 2 Register
Timer Output Compare 2 Register
ADCCSR
ADCDRH
ADCDRL
Control/Status Register
Data High Register
Data Low Register
Reset
status
00h(2)
00h
00h
xxh
0xh
00h
00h
FFh
FFh
FFh
FFh
00h
00h
00h
FFh
0xh
00h
7Fh
7Fh
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
xxh
00h
FCh
FCh
xxh
00h
00h
00h
00h
Remarks(1)
R/W(3)
R/W(3)
R/W(3)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
Read Only
Read Only
R/W
Read Only
Read Only
Read Only
R/W
R/W
Read Only
Read Only
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Doc ID 12468 Rev 3
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