ST72361J4-AUTO View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72361J4-AUTO

8-bit MCU for automotive with Flash or ROM, 10-bit ADC, 5 timers, SPI, LINSCI™

STMicroelectronics 

Supply, reset and clock management

The reset vector fetch phase duration is two clock cycles.

Figure 12. RESET sequence phases

RESET

Active Phase

INTERNAL RESET

256 or 4096 CLOCK CYCLES

FETCH

VECTOR

ST72361xx-Auto

5.5.2

Asynchronous external RESET pin

The RESET pin is both an input and an open-drain output with integrated RON weak pull-up

resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It

can be pulled low by external circuitry to reset the device. See Chapter 20: Electrical

characteristics for more details.

A reset signal originating from an external source must have a duration of at least th(RSTL)in

in order to be recognized (see Figure 14). This detection is asynchronous and therefore the

MCU can enter reset state even in HALT mode.

Figure 13. Reset block diagram

RESET

VDD

RON

Filter

INTERNAL

RESET

PULSE

GENERATOR

WATCHDOG RESET

LVD RESET

5.5.3

5.5.4

The RESET pin is an asynchronous signal which plays a major role in EMS performance. In

a noisy environment, it is recommended to follow the guidelines mentioned in the electrical

characteristics section.

External power-on reset

If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must

ensure by means of an external reset circuit that the reset signal is held low until VDD is over

the minimum level specified for the selected fOSC frequency.

A proper reset signal for a slow rising VDD supply can generally be provided by an external

RC network connected to the RESET pin.

Internal low voltage detector (LVD) reset

Two different reset sequences caused by the internal LVD circuitry can be distinguished:

● Power-on reset

● Voltage drop reset

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Doc ID 12468 Rev 3

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