ADSP-BF518KSWZ-ENG View Datasheet(PDF) - Analog Devices
Part Name
Description
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ADSP-BF518KSWZ-ENG Datasheet PDF : 62 Pages
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ADSP-BF512/BF514/BF516/BF518 (F)
includes support for five to eight data bits, one or two stop bits,
and none, even, or odd parity. Each UART port supports two
modes of operation:
• PIO (programmed I/O) – The processor sends or receives
data by writing or reading I/O mapped UART registers.
The data is double-buffered on both transmit and receive.
• DMA (direct memory access) – The DMA controller trans-
fers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
Each UART port's baud rate, serial data format, error code gen-
eration and status, and interrupts are programmable:
• Supporting bit rates ranging from (fSCLK/1,048,576) to
(fSCLK/16) bits per second.
• Supporting data formats from seven to 12 bits per frame.
• Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
The UART port’s clock rate is calculated as:
UART Clock Rate
=
------------------f--S--C---L---K-------------------
16 × UART_Divisor
Where the 16-bit UART_Divisor comes from the UART_DLH
(most significant 8 bits) and UART_DLL (least significant
8 bits) registers.
In conjunction with the general-purpose timer functions, auto-
baud detection is supported.
The capabilities of the UARTs are further extended with sup-
port for the infrared data association (IrDA®) serial infrared
physical layer link specification (SIR) protocol.
TWI CONTROLLER INTERFACE
The processors include a two wire interface (TWI) module for
providing a simple exchange method of control data between
multiple devices. The TWI is compatible with the widely used
I2C® bus standard. The TWI module offers the capabilities of
simultaneous master and slave operation, support for both 7-bit
addressing and multimedia data arbitration. The TWI interface
utilizes two signals for transferring clock (SCL) and data (SDA)
and supports the protocol at speeds up to 400k bits/sec. The
TWI interface signals are compatible with 5 V logic levels.
Additionally, the processor’s TWI module is fully compatible
with serial camera control bus (SCCB) functionality for easier
control of various CMOS camera sensor devices.
Preliminary Technical Data
RSI INTERFACE
The removable storage interface (RSI) controller acts as the host
interface for multi-media cards (MMC), secure digital memory
cards (SD Card), secure digital input/output cards (SDIO), and
CE-ATA hard disk drives. The following list describes the main
features of the RSI controller.
• Support for a single MMC, SD memory, SDIO card or CE-
ATA hard disk drive
• Support for 1-bit and 4-bit SD modes
• Support for 1-bit, 4-bit and 8-bit MMC modes
• Support for 4-bit and 8-bit CE-ATA hard disk drives
• A ten-signal external interface with clock, command, and
up to eight data lines
• Card detection using one of the data signals
• Card interface clock generation from SCLK
• SDIO interrupt and read wait features
• CE-ATA command completion signal recognition and
disable
10/100 ETHERNET MAC
The ADSP-BF516/BF518 processors offer the capability to
directly connect to a network by way of an embedded fast Ether-
net media access controller (MAC) that supports both 10-BaseT
(10M bits/sec) and 100-BaseT (100M bits/sec) operation. The
10/100 Ethernet MAC peripheral on the processor is fully com-
pliant to the IEEE 802.3-2002 standard and it provides
programmable features designed to minimize supervision, bus
use, or message processing by the rest of the processor system.
Some standard features are:
• Support of MII and RMII protocols for external PHYs
• Full duplex and half duplex modes
• Data framing and encapsulation: generation and detection
of preamble, length padding, and FCS
• Media access management (in half-duplex operation): col-
lision and contention handling, including control of
retransmission of collision frames and of back-off timing
• Flow control (in full-duplex operation): generation and
detection of pause frames
• Station management: generation of MDC/MDIO frames
for read-write access to PHY registers
• SCLK operating range down to 25 MHz (active and sleep
operating modes)
• Internal loopback from transmit to receive
Some advanced features are:
• Buffered crystal output to external PHY for support of a
single crystal system
• Automatic checksum computation of IP header and IP
payload fields of Rx frames
• Independent 32-bit descriptor-driven receive and transmit
DMA channels
Rev. PrE | Page 12 of 62 | March 2009
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