ADSP-BF518KSWZ-ENG View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-BF518KSWZ-ENG

Blackfin Embedded Processor

Analog Devices 

Preliminary Technical Data

• Frame status delivery to memory through DMA, including

frame completion semaphores for efficient buffer queue

management in software

• Tx DMA support for separate descriptors for MAC header

and payload to eliminate buffer copy operations

• Convenient frame alignment modes support even 32-bit

alignment of encapsulated receive or transmit IP packet

data in memory after the 14-byte MAC header

• Programmable Ethernet event interrupt supports any com-

bination of:

• Selected receive or transmit frame status conditions

• PHY interrupt condition

• Wakeup frame detected

• Selected MAC management counter(s) at half-full

• DMA descriptor error

• 47 MAC management statistics counters with selectable

clear-on-read behavior and programmable interrupts on

half maximum value

• Programmable receive address filters, including a 64-bin

address hash table for multicast and/or unicast frames, and

programmable filter modes for broadcast, multicast, uni-

cast, control, and damaged frames

• Advanced power management supporting unattended

transfer of receive and transmit frames and status to/from

external memory via DMA during low-power sleep mode

• System wakeup from sleep operating mode upon magic

packet or any of four user-definable wakeup frame filters

• Support for 802.3Q tagged VLAN frames

• Programmable MDC clock rate and preamble suppression

• In RMII operation, seven unused signals may be config-

ured as GPIO signals for other purposes

IEEE 1588 SUPPORT

The IEEE 1588 standard is a precision clock synchronization

protocol for networked measurement and control systems. The

ADSP-BF518/ADSP-BF518F processors include hardware sup-

port for IEEE 1588 with an integrated precision time protocol

synchronization engine (PTP_TSYNC). This engine provides

hardware assisted time stamping to improve the accuracy of

clock synchronization between PTP nodes. The main features of

the PTP_SYNC engine are:

• Support for both IEEE 1588-2002 and IEEE 1588-2008 pro-

tocol standards

• Hardware assisted time stamping capable of 12.5 ns

resolution

• Lock adjustment

• Programmable PTM message support

• Dedicated interrupts

• Programmable alarm

ADSP-BF512/BF514/BF516/BF518 (F)

• Multiple input clock sources (SCLK, MII clock, external

clock up to 50 MHz)

• Programmable pulse per second (PPS) output

• Auxiliary snapshot to time stamp external events

PORTS

Because of the rich set of peripherals, the processors group the

many peripheral signals to four ports—port F, port G, port H,

and port J. Most of the associated pins/balls are shared by multi-

ple signals. The ports function as multiplexer controls.

General-Purpose I/O (GPIO)

The ADSP-BF512/BF514/BF516/BF518(F) processors have 40

bidirectional, general-purpose I/O (GPIO) signals allocated

across three separate GPIO modules—PORTFIO, PORTGIO,

and PORTHIO, associated with Port F, Port G, and Port H,

respectively. Each GPIO-capable signal shares functionality

with other peripherals via a multiplexing scheme; however, the

GPIO functionality is the default state of the device upon

power-up. Neither GPIO output nor input drivers are active by

default. Each general-purpose port signal can be individually

controlled by manipulation of the port control, status, and

interrupt registers:

• GPIO direction control register – Specifies the direction of

each individual GPIO signal as input or output.

• GPIO control and status registers – The processor employs

a “write one to modify” mechanism that allows any combi-

nation of individual GPIO signals to be modified in a single

instruction, without affecting the level of any other GPIO

signals. Four control registers are provided. One register is

written in order to set signal values, one register is written

in order to clear signal values, one register is written in

order to toggle signal values, and one register is written in

order to specify a signal value. Reading the GPIO status

register allows software to interrogate the sense of the

signals.

• GPIO interrupt mask registers – The two GPIO interrupt

mask registers allow each individual GPIO signal to func-

tion as an interrupt to the processor. Similar to the two

GPIO control registers that are used to set and clear indi-

vidual signal values, one GPIO interrupt mask register sets

bits to enable interrupt function, and the other GPIO inter-

rupt mask register clears bits to disable interrupt function.

GPIO signals defined as inputs can be configured to gener-

ate hardware interrupts, while output signals can be

triggered by software interrupts.

• GPIO interrupt sensitivity registers – The two GPIO inter-

rupt sensitivity registers specify whether individual signals

are level- or edge-sensitive and specify—if edge-sensitive—

whether just the rising edge or both the rising and falling

edges of the signal are significant. One register selects the

type of sensitivity, and one register selects which edges are

significant for edge-sensitivity.

Rev. PrE | Page 13 of 62 | March 2009

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