AD9775EB View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9775EB Datasheet PDF : 48 Pages
| |||
AD9775
PLL_LOCK
1 = LOCK
0 = NO LOCK
CLK+ CLK–
PLLVDD
AD9775
INTERPOLATION
FILTERS,
MODULATORS,
AND DACS
PHASE
DETECTOR
CHARGE
PUMP
LPF
1
INPUT
DATA
LATCHES
2
4
8
CLOCK
DISTRIBUTION
CIRCUITRY
INTERPOLATION
RATE
CONTROL
INTERNAL SPI
CONTROL
REGISTERS
SPI PORT
PRESCALER
VCO
MODULATION
RATE
CONTROL
PLL DIVIDER
(PRESCALER)
CONTROL
PLL
CONTROL
(PLL ON)
Figure 12. PLL and Clock Circuitry with PLL Enabled
PLL_LOCK
1 = LOCK
0 = NO LOCK
CLK+ CLK–
AD9775
INTERPOLATION
FILTERS,
MODULATORS,
AND DACS
PHASE
DETECTOR
CHARGE
PUMP
1
INPUT
DATA
LATCHES
24 8
CLOCK
DISTRIBUTION
CIRCUITRY
INTERPOLATION
RATE
CONTROL
INTERNAL SPI
CONTROL
REGISTERS
SPI PORT
PRESCALER
VCO
MODULATION
RATE
CONTROL
PLL DIVIDER
(PRESCALER)
CONTROL
PLL
CONTROL
(PLL ON)
Figure 13. PLL and Clock Circuitry with PLL Disabled
In addition, if the zero stuffing option is enabled, the VCO will
double its speed again. Phase noise may be slightly higher with
the PLL enabled. Figure 14 illustrates typical phase noise per-
formance of the AD9775 with 2× interpolation and various
input data rates. The signal synthesized for the phase noise
measurement was a single carrier at a frequency of fDATA/4. The
repetitive nature of this signal eliminated quantization noise and
distortion spurs as a factor in the measurement. Although the
curves blend together in Figure 14, the different conditions are
called out here for clarity.
fDATA
125 MSPS
125 MSPS
100 MSPS
75 MSPS
50 MSPS
PLL
Disabled
Enabled
Enabled
Enabled
Enabled
Prescaler Ratio
div1
div2
div2
div4
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
1
2
3
4
5
FREQUENCY OFFSET – MHz
Figure 14. Phase Noise Performance
It is important to note that the resistor/capacitor needed for the
PLL loop filter is internal on the AD9775. This will suffice unless
the input data rate is below 10 MHz, in which case an external
series RC is required between the LPF and PLLVDD pins.
POWER DISSIPATION
The AD9775 has three voltage supplies: AVDD, DVDD, and
CLKVDD. Figures 15, 16, and 17 show the current required
from each of these supplies when each is set to the 3.3 V nominal
specified for the AD9775. Power dissipation (PD) can easily be
extracted by multiplying the given curves by 3.3. As Figure 15
shows, IDVDD is very dependent on the input data rate, the interpo-
lation rate, and the activation of the internal digital modulator.
IDVDD, however, is relatively insensitive to the modulation rate
by itself. In Figure 16, IAVDD shows the same type of sensitivity
to the data, the interpolation rate, and the modulator function
but to a much lesser degree (<10%). In Figure 17, ICLKVDD
varies over a wide range yet is responsible for only a small per-
centage of the overall AD9775 supply current requirements.
400
8؋, (MOD. ON)
350
4؋, (MOD. ON)
2؋, (MOD. ON)
300
250
8؋
4؋
2؋
200
150
100
1؋
50
0
0
50
100
150
200
fDATA – MHz
Figure 15. IDVDD vs. fDATA vs. Interpolation Rate,
PLL Disabled
REV. 0
–21–
Share Link: 