AD9775EB View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9775EB Datasheet PDF : 48 Pages
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AD9775
tOD
CLKIN
DATACLK
DATA AT PORTS
1 AND 2
tS tH
tS = 0.0ns
tH = 2.5ns
(TYP SPECS)
Figure 18. Timing Requirements in Two Port
Input Mode, with PLL Enabled
DATACLK DRIVER STRENGTH
(Control Register 02h, Bit 5)
The DATACLK output driver strength is capable of driving
>10 mA into a 330 Ω load while providing a rise time of 3 ns.
Figure 19 shows DATACLK driving a 330 Ω resistive load at a
frequency of 50 MHz. By enabling the drive strength option
(Control Register 02h, Bit 5), the amplitude of DATACLK
under these conditions will be increased by approximately 200 mV.
3.0
2.5
2.0
1.5
1.0
to the internal input data rate of the I and Q channels. The
selection of the data for the I or the Q channel is determined by the
state of the logic level at Pin 31 (IQSEL when the AD9775 is in
one port mode) on the rising edge of ONEPORTCLK. IQSEL
= 1 under these conditions will latch the data into the I channel
on the clock rising edge, while IQSEL = 0 will latch the data into
the Q channel. It is possible to invert the I and Q selection by set-
ting control Register 02h, Bit 1 to the invert state (Logic “1”).
Figure 20 illustrates the timing requirements for the data inputs as
well as the IQSEL input. Note that the 1× interpolation rate is
not available in the one port mode.
The DAC output sample rate in one port mode is equal to CLKIN
multiplied by the interpolation rate. If zero stuffing is used, another
factor of two must be included to calculate the DAC sample rate.
ONEPORTCLK INVERSION
(Control Register 02h, Bit 2)
By programming this bit, the ONEPORTCLK signal shown in
Figure 20 can be inverted. With inversion enabled, tOD refers to
the delay between the rising edge of the external clock and the
falling edge of ONEPORTCLK. The setup and hold times, tS
and tH, will be with respect to the falling edge of ONEPORTCLK.
There will be no other effect on timing.
ONEPORTCLK DRIVER STRENGTH
The drive capability of ONEPORTCLK is identical to that of
DATACLK in the two port mode. Refer to Figure 19 for perfor-
mance under load conditions.
tOD
CLKIN
tOD = 4.7ns
tS = 3.0ns
tH = –0.5ns
tIQS = 3.5ns
tIQH = –1.5ns
ONEPORTCLK
0.5
0
–0.5
0
DELTA APPROX. 2.8ns
10
20
30
40
50
TIME – ns
Figure 19. DATACLK Driver Capability into 330 Ω
at 50 MHz
PLL ENABLED, ONE PORT MODE
(Control Register 02h, Bits 6–1 and 04h, Bits 7–1)
In one port mode, the I and Q channels receive their data from an
interleaved stream at digital input Port 1. The function of Pin 32
is defined as an output (ONEPORTCLK) that generates a clock at
the interleaved data rate which is 2× the internal input data
rate of the I and Q channels. The frequency of CLKIN is equal
I AND Q INTERLEAVED
INPUT DATA AT PORT 1
tS tH
IQSEL
tIQS
tIQH
Figure 20. Timing Requirements in One Port
Input Mode with the PLL Enabled
REV. 0
–23–
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