STLC5464 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STLC5464

MULTI-HDLC WITH n x 64 SWITCHING MATRIX ASSOCIATED

STMicroelectronics 

STLC5464

III - FUNCTIONAL DESCRIPTION (continued)

III.2.5 - Transparent Modes

In the transparentmode, the Multi-HDLC transmits

data in a completely transparent manner without

performing any bit manipulation or Flag insertion.

The transparent mode is per byte function.

Two transparent modes are offered :

- First mode : for the receive channels, the

Multi-HDLC continuously writes received bytes

into the external memory as specified in the cur-

rent receive descriptor without taking intoaccount

the Fill Character Register.

- Secondmode: the Fill CharacterRegister specifies

the ”fill character”which must be taken into account.

In reception,the ”fill character”will not betransferred

to theexternalmemory. Thedetectionof ”Fill charac-

ter” marks the end of a message and generates an

interruptifBINT=1 (see TransmitDescriptoronPage

78). When the ”Fill character”is not detected a new

message is receiving.

As for the HDLC mode the correspondence

between the physical time slot and the logical

channel is fully defined in the Time Slot Assigner

memory (Time slot used or not used, logical chan-

nel number, source, destination).

III.2.6 - Command of the HDLC Channels

The microprocessor is able to control each HDLC

receive and transmit channel. Some of the com-

mands are specific to the transmission or the re-

ception but others are identical.

III.2.6.1 - Reception Control

The configuration of the controller operating mode

is: HDLC mode or Transparent mode.

The control of the controller: START, HALT, CON-

TINUE, ABORT.

- START : On a start command, the RxDMA con-

troller reads the address of the first descriptor in

the initialization block memory and is ready to

receive a frame.

- HALT : For overloading reasons, the microproc-

essor can decide to halt the reception. The DMA

controller finishes transfer of the current frame to

external memory and stops. The channel can be

restarted on CONTINUE command.

- CONTINUE : The reception restarts in the next

descriptor.

- ABORT: On an abort command, the reception is

instantaneously stopped. The channel can be

restarted on a START or CONTINUE command.

Reception of FLAG (01111110) or IDLE (11111111)

between Frames.

Address recognition. The microprocessor defines

26/83

the addressesthat the Rx controller has to take into

account.

In transparent mode: ”fill character” register se-

lected or not.

III.2.6.2 - Transmission Control

The configuration of the controller operating mode

is : HDLC mode or Transparent mode.

The control of the controller : START, HALT, CON-

TINUE, ABORT.

- START : On a start command, the Tx DMAcontrol-

ler reads the address of the first descriptor in the

initialization block memory and tries to transmit the

first frame if End Of Queue is not at ”1”.

- HALT : The transmitter finishes to send the cur-

rent frame and stops.The channel can be restart-

ed on a CONTINUE command.

- CONTINUE : if the CONTINUE command occurs

after HALT command, the HDLC Transmitter re-

starts by transmitting the next buffer associated

to the next descriptor.

If the CONTINUE command occurs after an

ABORT command which has occurred during a

frame, the HDLC transmitter restarts by transmit-

ting the frame which has been effectively aborted

by the microprocessor.

- ABORT: On an abort command, the transmission

of the current frame is instantaneously stopped,

an ABORT sequence ”1111111” is sent, followed

by IDLE or FLAG bytes. The channel can be

restarted on a START or CONTINUE command.

Transmission of FLAG (01111110 ) or IDLE

(111111111)between frames can be selected.

CRC can be generated or not. If the CRC is not

generated by the HDLC Controller, it must be lo-

cated in the shared memory.

In transparentmode: ”fill character” register can be

selected or not.

III.3 - C/I and Monitor

III.3.1 - Function Description

The Multi-HDLC is able to operate both GCI and V*

links. The TDM DIN/DOUT 4 and 5 are internally

connected to the CI and Monitor receivers/trans-

mitters. Since the controllershandle up to 16CI and

16 Monitor channels simultaneously, the Multi-

HDLC can manage up to 16 level 1 circuits.

The Multi-HDLC can be used to support the CI and

monitor channels based on the following proto-

cols :

- ISDN V* protocol

- ISDN GCI protocol

- Analog GCI protocol.

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