STLC5464 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STLC5464

MULTI-HDLC WITH n x 64 SWITCHING MATRIX ASSOCIATED

STMicroelectronics 

STLC5464

III - FUNCTIONAL DESCRIPTION (continued)

III.5 - Memory Interface

III.5.1 - Function Description

The memory interface allows the connection of

Static or Dynamic RAM. The memory space ad-

dressable in the two configurationsis not thesame.

In the case of dynamic memory (DRAM), the mem-

ory interface will address up to 16 Megabytes. In

caseof staticmemory(SRAM) only 1 Megabytewill

be addressed. The memory location is always or-

ganized in 16 bits.

The memory is shared between the Multi-HDLC

and the microprocessor. Theaccess to the memory

is arbitrated by an internal function of the circuit:

the bus arbitration.

Example 1 : if the applicationrequires 16 bit mProc-

essor and 1 Megaword Shared memory size, three

capabilities are offered :

- 4 DRAM Circuits (256Kx16) or

- 4 DRAM Circuits (1Mx4) or

- 1 DRAM Circuit (1Mx16).

Example 2 : if the application requires 8 bit mProc-

essor and 1 Megabyte Shared memory size, three

capabilities are offered:

- 2 DRAM Circuits (256Kx16) or

- 8 SRAM Circuits (128Kx8) or

- 2 SRAM Circuits (512kx8).

Example 3 : for small applications it is possible to

connect 2 SRAM Circuits (128Kx8) to obtain 256

Kilobytes shared memory.

III.5.2 - Choice of memory versus microproc-

essor and capacity required

The memory interface depends on the memory

chips which are connected. As the memory chips

will be chosen versus the microprocessor and the

wanted memory space, the Table 22 presents the

different configurations.

III.5.3 - Memory Cycle

For SRAM and DRAM, the different cycles are

programmable (see Paragraph ”Memory Interface

Configuration Register MICR (32)H” on Page 71).

Each cycle is equal to : p x 1/f

with f the frequencyof signal applied to the Crystal

1 input and p selected by the user.

Table 22 : DRAM and SDRAM Selection versus µP

Microprocessor and

shared memory

Shared memory size required by the application

8 bits

Number of

µProcessor Megabytes

0.5

1

2

4

8

16

16 bits

Number of

µProcessor Megawords

0.25

0.5

1

2

4

8

DRAM Circuits proposed

Capacity Organization

4 Megabits 256Kx16

1Mx4

16 Megabits 1Mx16

4Mx4

64 Megabits 4Mx16

SRAM Circuits proposed

Capacity Organization

1 Megabits 128Kx8

4 Megabits 512kx8

1(256Kx16)

4(128Kx8)

2(256Kx16)

8(128Kx8)

2(512kx8)

4(256Kx16)

4(1Mx4)

1(1Mx16)

8(1Mx4)

2(1Mx16)

16(1Mx4)

4(1Mx16)

4(4Mx4)

1(4Mx16)

Not possible

8(4Mx4)

2(4Mx16)

31/83

Share Link: