STLC5464 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STLC5464 Datasheet PDF : 83 Pages
| |||
STLC5464
V - CLOCK TIMING (continued)
V.2 - TDM Synchronization
Figure 28 : Synchronization Signals received by the Multi-HDLC
CLOCK A (o r B)
t2
DCLK de live re d by
the Multi-HDLC
FSCG d e livere d by
the Multi-HDLC
t1
t3
t4
t5
t6
DOUT0/7, CB
DIN0/8
ECHO
Bit 7, Time S lot 31
Bit 0, Time Slot 0
t7
t7
t9
t8
The four Multiplex Configura tion Re giste rs a re a t z e ro (no de lay be twe e n FS a nd Multiplexe s).
Symbol
t1
t2
t3
t4
t5
t6
t7
t7
t8
t9
Parameter
Clock Period if 4096kHz
Clock Period if 2048kHz
Delay between CLOCK A or B and DCLK (30pF)
Set-up Time FS/DCLK
Hold Time FS/DCLK
Duration FS
DCLK to Data 50pF
DCLK to Data 100pF
Set-up Time Data/DCLK
Hold Time Data/DCLK
Set-up Echo/DCLK (rising edge)
Hold Time Echo/DCLK (rising edge)
Min.
Id CLOCKA or B
20
20
244
20
20
205
Typ.
244
488
5
Max.
Id CLOCKA or B
30
t1-20
125000-244
50
100
155
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
39/83
Share Link: 