STLC5464 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STLC5464

MULTI-HDLC WITH n x 64 SWITCHING MATRIX ASSOCIATED

STMicroelectronics 

STLC5464

III - FUNCTIONAL DESCRIPTION (continued)

III.5.4 - SRAM interface

Signals

NCE7

NCE6

A19 A18

1

1

1

1

A0 or equiv.

1

0

NCE5

1

0

1

NCE4

1

0

0

NCE3

0

1

1

NCE2

0

1

0

NCE1

0

0

1

NCE0

0

0

0

The SRAM space achieves 1 Mbyte max. It is

always organized in 16 bits. The structure of the

memory plane is shown in the following figures.

Because of the different chips usable, 19 address

wires and 8 NCE (Chip Enable) are necessary to

address the 1 Mbyte. The NCE selects the Most or

Least Significant Byte versus the value of A0 deliv-

ered by the µP and the location of chip in the

memory space.

III.5.4.1 - 18K x n SRAM

The Address bits delivered by the Multi-HDLC for

128K x n SRAM circuits are :

ADM0/14 and ADM15/16 (17 bits) corresponding

with A1/17 delivered by the µP.

Figure 18 : 128K x 8 SRAM Circuit Memory

Organization

128K x 16

128K x 8

NCE 7

7

NCE 6

6

NCE 5

5

NCE 4

4

NCE 3

3

NCE 2

2

NCE 1

1

NCE 0

DM8/15

0

DM0/7

III.5.4.2 - 512K x n SRAM

Signals

NCE1

NCE0

A0 or equiv.

1

0

The Address bits delivered by the Multi-HDLC for

512K x n SRAM circuits are :

ADM0/14 and ADM15/18 (19 bits) corresponding

with A1/19 delivered by the µP.

32/83

Figure 19 : 512K x 8 SRAM Circuit Memory

Organization

512K x 16

512K x 8

NCE1

1

NCE0

0

DM8/15

DM0/7

III.5.5 - DRAM Interface

In DRAM, the memory space can achieve up to 16

megabytes organized by 16 bits. Eleven address

wires, four NRAS and two NCAS are needed to

select any byte in the memory. One NRAS signal

selects 1 bank of 4 and the NCAS signals select the

bytes concerned by the transfer (1 or 2 selecting a

byte or a word). The DRAM memory interface is

then defined. The ”RAS only” refresh cycles will

refresh all memory locations. The refresh is pro-

grammable. The frequency of the refresh is fixed

by the memory requirements.

III.5.5.1 - 256K x n DRAM Signals

Signals

A20 A19 A0 or equiv.

NRAS3

1

1

NRAS2

1

0

NRAS1

0

1

NRAS0

0

0

NCAS1

1

NCAS0

0

The Address bits delivered by the Multi-HDLC for

256K x n DRAM circuits are :

ADM0/8 (2 x 9 = 18 bits) corresponding with A1/18

delivered by the µP.

Figure 20 : 256K x 16 DRAM Circuit Organization

CAS1

CAS0

RAS 3

7

256K x 16

6

RAS 2

5

4

RAS 1

3

2

RAS 0

1

0

DM8/15

DM0/7

ADM0/8, NWE, NOE a re conne cte d to e a ch circuit.

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