STLC5464 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STLC5464 Datasheet PDF : 83 Pages
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STLC5464
V - CLOCK TIMING
V.1 - Synchronization Signals delivered by the system
For one of three different input synchronizations which is programmed, FSCG and FSCV* signals
delivered by the Multi-HDLC are in accordance with the figure hereafter.
Figure 27 : Clocks received and delivered by the Multi-HDLC
CLOCK B
CLOCK A
t2
t5h
t5l
t1
3
4
5
6
7
0
1
1) S y Mode
F ra me A (or B)
t3
t4
2) G CI Mode
F ra me A (or B)
t3
t4
t3
t4 CGI
3) V*Mod e
F ra me A (or B)
DIN 0/8, ECHO
DO UT 0/7, CB
Bit3
if F S = F S CG
TDM0/7
F S CG delivere d
by the circuit
F S CV* de livere d
by the circuit
Bit4
Bit5
Bit6
Time S lot 31
Bit7
Bit0
Bit1
Time S lot 0
The four Multiplex Configura tion Registers are a t zero (no de lay).
Symbol
t1
t2
t3
t4
t4GCI
t5
Parameter
Clock Period if 4096kHz
Clock Period if 8192kHz
Delay between Clock A and Clock B
Set up time Frame A (or B)/CLOCK A (or B)
Hold time Frame A (or B)/CLOCK A (or B)
Clock ratio t5h/t5l
Min.
239
120
- 60
10
10
10
75
Typ.
244
122
0
100
Max.
249
125
+60
t1-10
t1-10
125000 - (t1 - 10)
125
Unit
ns
ns
ns
ns
ns
%
38/83
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