LNBS21PD(2002) View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
LNBS21PD
(Rev.:2002)
(Rev.:2002)
STMicroelectronics
LNBS21PD Datasheet PDF : 19 Pages
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LNBS21
LNBS1 SOFTWARE DESCRIPTION
INTERFACE PROTOCOL
The interface protocol comprises:
- A start condition (S)
CHIP ADDRESS
MSB
S000100
ACK= Acknowledge
S= Start
P= Stop
R/W= Read/Write
- A chip address byte = hex 10 / 11 (the LSB bit
determines read(=1)/write(=0) transmission)
- A sequence of data (1 byte + acknowledge)
- A stop condition (P)
DATA
LSB
MSB
0 R/W ACK
LSB
ACK P
SYSTEM REGISTER (SR, 1 BYTE)
MSB
R, W
R, W
PCL
ISEL
R,W= read and write bit
R= Read-only bit
All bits reset to 0 at Power-On
R, W
TEN
R, W
LLC
TRANSMITTED DATA (I2C BUS WRITE MODE)
When the R/W bit in the chip address is set to 0,
the main µP can write on the System Register
(SR) of the LNBS21 via I2C bus. Only 6 bits out of
R, W
VSEL
R, W
EN
R
OTF
LSB
R
OLF
the 8 available can be written by the µP, since the
re-maining 2 are left to the diagnostic flags, and
are read-only.
PCL ISEL TEN LLC VSEL EN
0
0
1
0
1
1
1
0
1
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
X
X
X
X
X
0
X= don't care.
Values are typical unless otherwise specified
OTF
X
X
X
X
X
X
X
X
X
X
X
OLF
Function
X VOUT=13V, VUP=16V Loopthrough switch open
X VOUT=18V, VUP=21V Loopthrough switch open
X VOUT=14V, VUP=17V Loopthrough switch open
X VOUT=19V, VUP=22V Loopthrough switch open
X 22KHz tone is controlled by DSQIN pin
X 22KHz tone is ON, DSQIN pin disabled
X IOUT(min)=750mA, IOUT(max)=1A ISC=300mA
X IOUT(min)=600mA, IOUT(max)=900mA ISC=300mA
X Pulsed (dynamic) current limiting is selected
X Static current limiting is selected
X Power blocks disabled, Loopthrough switch closed
RECEIVED DATA (I2C bus READ MODE)
The LNBS21 can provide to the Master a copy of
the SYSTEM REGISTER information via I2C bus
in read mode. The read mode is Master activated
by sending the chip address with R/W bit set to 1.
At the following master generated clocks bits, the
LNBS21 issues a byte on the SDA data bus line
(MSB transmitted first).
At the ninth clock bit the MCU master can:
- acknowledge the reception, starting in this way
the transmission of another byte from the
LNBS21;
7/19
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