STM32F103V8H6TR Ver la hoja de datos (PDF) - STMicroelectronics

Número de pieza

componentes Descripción

Fabricante

STM32F103V8H6TR

Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces

STMicroelectronics 

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Figure 31. Synchronous non-multiplexed PSRAM write timings

tw(CLK)

tw(CLK)

BUSTURN = 0

FSMC_CLK

td(CLKL-NExL)

FSMC_NEx

Data latency = 1

td(CLKH-NExH)

td(CLKL-NADVL)

FSMC_NADV

td(CLKL-NADVH)

FSMC_A[25:0]

FSMC_NWE

td(CLKL-AV)

td(CLKL-NWEL)

td(CLKH-AIV)

td(CLKH-NWEH)

FSMC_D[15:0]

td(CLKL-Data)

td(CLKL-Data)

D1

D2

FSMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b)

tsu(NWAITV-CLKH)

FSMC_NBL

td(CLKL-NBLH)

th(CLKH-NWAITV)

ai14993e

Table 38. Synchronous non-multiplexed PSRAM write timings(1)(2)

Symbol

Parameter

Min

Max Unit

tw(CLK)

FSMC_CLK period

27.7

ns

td(CLKL-NExL)

FSMC_CLK low to FSMC_NEx low (x = 0...2)

2

ns

td(CLKH-NExH)

FSMC_CLK high to FSMC_NEx high (x = 0...2)

THCLK + 2

ns

td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low

4

ns

td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high

5

ns

td(CLKL-AV)

FSMC_CLK low to FSMC_Ax valid (x = 16...25)

0

ns

td(CLKH-AIV)

FSMC_CLK high to FSMC_Ax invalid (x = 16...25) TCK + 2

ns

td(CLKL-NWEL)

FSMC_CLK low to FSMC_NWE low

1

ns

td(CLKH-NWEH) FSMC_CLK high to FSMC_NWE high

THCLK + 1

ns

td(CLKL-Data)

FSMC_D[15:0] valid data after FSMC_CLK low

6

ns

tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high

7

ns

th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high

2

ns

td(CLKL-NBLH)

FSMC_CLK low to FSMC_NBL high

1

ns

1. CL = 15 pF.

2. Based on characterization, not tested in production.

Doc ID 14611 Rev 7

71/123

Share Link: