ST72652 データシートの表示（PDF） - STMicroelectronics

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ST72652

LOW-POWER, FULL-SPEED USB 8-BIT MCU WITH 32K FLASH, 5K RAM, FLASH CARD I/F, TIMER, PWM, ADC, I2C, SPI

STMicroelectronics 

ST7265x

13.9 CONTROL PIN CHARACTERISTICS

13.9.1 Asynchronous RESET Pin

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ 1)

Max

Unit

VIL

VIH

Vhys

VOL

Input low level voltage 2)

Input high level voltage 2)

Schmitt trigger voltage hysteresis 3)

Output low level voltage 4)

RON Weak pull-up equivalent resistor 5)

tw(RSTL)out Generated reset pulse duration

th(RSTL)in External reset pulse hold time 6)

tg(RSTL)in Filtered glitch duration 7)

VDD=5V

VDD=5V

VSS

0.7xVDD

VDD=5V

IIO=+5mA

IIO=+2mA

VIN=VSS

VDD=5V

VDD=3.3V

70

130

External pin or

internal reset sources

20

400

0.68

0.28

100

200

4

0.3xVDD

V

VDD

mV

0.95

V

0.45

130

kΩ

260

1/fSFOSC

µs

100

ns

8F)igure 97. Typical Application with RESET pin

OPTIONAL

EXTERNAL

RESET

CIRCUIT 8)

VDD

VDD

0.1µF 4.7kΩ

0.1µF

VDD

RON

RESET

ST72XXX

INTERNAL

RESET CONTROL

WATCHDOG RESET

LVD RESET

Notes:

1. Unless otherwise specified, typical data are based on TA=25°C and VDD=5V.

2. Data based on characterization results, not tested in production.

3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

4. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO

(I/O ports and control pins) must not exceed IVSS. Not tested in production.

5. The RON pull-up equivalent resistor is based on a resistive transistor (corresponding ION current characteristics de-

scribed in Figure 97). This data is based on characterization results, not tested in production.

6. All short pulse applied on RESET pin with a duration below th(RSTL)in can be ignored.

7. The reset network protects the device against parasitic resets, especially in a noisy environment.

8. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device

can be damaged when the ST7 generates an internal reset (LVD or watchdog).

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