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ST72652 データシートの表示(PDF) - STMicroelectronics

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ST72652 Datasheet PDF : 166 Pages
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ST7265x
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
Figure 100. SPI Slave Timing Diagram with CPHA=11)
SS INPUT
tsu(SS)
tc(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO)
tw(SCKH)
tw(SCKL)
tv(SO)
MISO OUTPUT
see
note 2
HZ
tsu(SI)
MSB OUT
th(SI)
BIT6 OUT
th(SS)
th(SO)
tr(SCK)
tf(SCK)
LSB OUT
MOSI INPUT
MSB IN
BIT1 IN
LSB IN
Figure 101. SPI Master Timing Diagram 1)
SS INPUT
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tc(SCK)
tsu(MI)
th(MI)
tw(SCKH)
tw(SCKL)
MISO INPUT
tv(MO)
MSB IN
th(MO)
BIT6 IN
tr(SCK)
tf(SCK)
LSB IN
MOSI OUTPUT see note 2
MSB OUT
BIT6 OUT
LSB OUT
tdis(SO)
see
note 2
see note 2
Notes:
1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
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