STPCI2GDYI(2002) データシートの表示（PDF） - STMicroelectronics

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STPCI2GDYI
(Rev.:2002)

X86 Core PC Compatible System-on-Chip for Terminals

STMicroelectronics 

STRAP OPTION

3.1.2. STRAP REGISTER 1

This register is read only.

STRAP1

Access = 0022h/0023h

Regoffset =04Bh

7

6

5

4

3

2

1

0

MD[40]

MD[14]

RSV

RSV

RSV

RSV

RSV

MD[36]

This register defaults to the values sampled on the MD pins after reset

Bit Number Sampled

Bits 7-6

Bits 5-1

Bit 0

Mnemonic

MD[40] & MD[14]

Rsv

MD[36]

Description

CPU Clock Multiplication (486 mode):

MD14 MD40

1 0 X1

1 1 X2

All other settings are reserved

HCLK maximum speed is 66MHz and in CPU mode X2.

Operation in X1 mode is only guaranteed up to 66MHz.

Reserved

These bits reflect the values sampled on MD[36] and determines the

Local Bus Boot device width:

0: 8-bit Boot Device

1: 16-bit Boot Device

36/111

Issue 1.0 - July 24, 2002

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