STPCI2GDYI(2002) データシートの表示（PDF） - STMicroelectronics
部品番号
コンポーネント説明
メーカー
STPCI2GDYI Datasheet PDF : 111 Pages
| |||
STRAP OPTION
3.1.3. HCLK PLL STRAP REGISTER
This register is read only.
HCLK_STRAP0
7
RSV
Access = 0022h/0023h
Regoffset =05Fh
6
5
4
3
2
1
0
MD[26]
MD[25]
MD[24]
RSV
This register defaults to the values sampled on the MD pins after reset
Bit Number Sampled
Bits 7-6
Bits 5-3
Bits 2-0
Mnemonic
Rsv
MD[26:24]
Rsv
Description
These bits are fixed to ‘0’
These pins reflect the values sampled on MD[26:24] pins respectively
and control the Host clock frequency synthesizer as shown in Table 3-1
Reserved
MD[3]
0
0
0
0
Table 3-1. HCLK Frequency Configuration
MD[2]
0
0
0
0
MD[26]
MD[25]
0
0
0
0
0
1
0
1
All other settings are reserved
MD[24]
0
1
0
1
HCLK Speed
25 MHz
50 MHz
60 MHz
66 MHz
Issue 1.0 - July 24, 2002
37/111
Share Link: 