CL-PS7500FE データシートの表示（PDF） - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

external latches/drivers to extend the I/O data by 16 bits. The upper halfword of the CL-PS7500FE data

bus is routed through these external devices if present. This type of I/O access is used for the address

space from 03010000 to 0302CFFF (five sections), and in the larger extended address space from

0x08000000 to 0x0FFFFFFF (eight sections). There are four fixed cycle types based on the 16-MHz

clock, although the larger extended address area only supports two of these cycle types. Any access may

be held up by external circuitry removing the READY signal before the end of the cycle.

The signals that control the external buffers and latches required to implement 32-bit-wide I/O are:

q nWBE

q nRBE

q nBLO

For full details of the external circuitry and connections required to implement a 32-bit-wide I/O system

using the CL-PS7500FE, refer to Appendix D.

Two additional inputs are provided to allow external circuitry to route a full 32-bit data word through the

16-bit I/O bus using multiplexing:

q nXIPLATCH

q nXIPMUX16

This would allow, for example, the execution of ARM code from a 16-bit-wide PCMCIA card with a suitable

external controller. The nXIPMUX16 signal directly controls an internal multiplexer that maps either the

upper or lower 16 bits of the internal data bus through to the 16-bit-wide I/O bus, for writes to an I/O periph-

eral.

When nXIPMUX16 is low, the upper 16 bits of the data bus are passed to BD[15:0], and when

nXIPMUX16 is high, the lower 16 bits of the data bus are passed to BD[15:0].

For reads from an I/O peripheral, the falling edge of the nXIPLATCH signal causes the first 16 bits pro-

vided on the BD[15:0] bus to be latched as the upper halfword for the main internal data bus, then the

lower 16 bits can be output from the peripheral and the I/O cycle can be allowed to complete normally. If

nXIPLATCH has been driven low, the upper halfword of data is driven to the ARM processor internally and

not from the external transceivers if present.

Depending on the cycle timing, it is usually necessary for the external controller to use the READY signal

to stretch the I/O access to give sufficient time for both half words to be read or written as appropriate. If

an I/O access is to be stretched, the READY signal must be set low before the end of the cycle as shown

in the timing diagrams. This causes the nIOR or nIOW strobe and the chip select to be held low until

READY is set back to high, when the I/O cycle complete as normal. READY is sampled on the rising edge

of the first 16-MHz cycle before the I/O cycle is due to complete.

The four address areas for 16-MHz I/O within the main I/O address space can support any of the four

available cycle types A-to-D. The IOTCR register can be programmed (at address 0x032000C4) to deter-

mine the type of cycle for each group of addresses. The addresses are grouped so that the nCCS and

pseudo DMA address spaces form one group, and the nPCCS1 and nPCCS2 address area forms another

group.

112

I/O SUBSYSTEMS

ADVANCE DATA BOOK v2.0

June 1997

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