CL-PS7500FE データシートの表示（PDF） - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

11.10.4 Control

The converter control register allows the discharge transistors and counters for each channel to be

enabled and disabled, to give full control over the resetting of the counter and the timing of the start of a

conversion cycle. Before a conversion can be started, the discharge bit and the counter clear bit for the

channel in question should be forced one and zero respectively, and then the bits should be returned to

zero and one respectively to actually initiate a conversion cycle. This causes the analog voltage across

the external capacitor to begin to ramp up, and simultaneously the 2-MHz clock to the counters is enabled,

thus starting the count.

Synchronization between the memory system clock used to program the registers, and the 2-MHz I/O

world clock results in a small extra delay before the counter is really enabled, but this is negligible against

the 0.5-µs period of the 2-MHz clock.

Address 0x032000E8 — Converter Control

76543210

DDDDCCCC

D[3:0]

C[3:0]

Write

Read

Reset

discharge transistor control for channels 4–1

clear counter for channels 4–1

bit[7:4]

0

transistor off

1

transistor on (discharge)

bit[3:0]

0

clear counter

1

enable counter

return above values

set all zero (clear counters and don’t discharge)

11.10.5 Comparators

The comparators are accurate to 2.5-mV resolution and require a stable reference voltage of less than

2.5 V to function correctly. The reference voltage is applied at the ATODREF pin. The same reference volt-

age is routed to all four comparators.

In order for the comparators to function correctly, it is essential that the reference current to the Video

DACs on the VIREF pin is present, as this current is used to generate the operating current used by the

gain stages in the comparator. The comparator reference currents are disabled to save power if all the

interrupt enables (bits 3:0 of the interrupt control register) are set to ‘0’. So, at least one channel must be

enabled for any of the channels to function correctly.

11.10.6 Converter Operation

The values of the capacitance and variable resistance used in the external RC circuit determine the range

of time delays seen from the moment the capacitor begins to charge to the moment that the comparator

threshold is crossed.

The 16-bit counters are clocked by the 2-MHz internal clock (derived from the 32-MHz I_OCLK), and thus

the counter counts for 65536 values over 32.7 ms before returning to zero. To provide a meaningful read-

ing from the converter, it is important that the capacitor and variable resistor values are such that this time

118

I/O SUBSYSTEMS

ADVANCE DATA BOOK v2.0

June 1997

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