CL-PS7500FE データシートの表示（PDF） - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

Internal register programming bursts can occur in blocks of up to four before re-arbitration occurs; this

takes 16 MEMCLK cycles. Burst mode ROM cycles are re-arbitrated after every four, so are sequential

DRAM accesses. Successive non-sequential accesses always allows DMA onto the bus. For this reason,

it is unlikely that these accesses are the cause of the worst-case DMA latency. However, it is possible to

use the ROM interface in half-speed mode, with the slowest ROM timing and a 16-bit-wide ROM, in which

case an access could take 28 internal MEMRFCK cycles. Under these circumstances the ROM interface

could be the limiting factor.

To determine the limiting factor in a system, calculate the number of cycles required for a worst case ROM

access. The number of cycles for each programmed value in ROMCR is shown below:

For a non-sequential access, programming ROMCR[2:0] to:

‘000’ – 7 cycles

‘001’ – 6 cycles For all:

‘010’ – 5 cycles Multiply by 2 if 16-bit mode set

‘011’ – 4 cycles Multiply by 2 if half-speed bit set

‘100’ – 3 cycles

‘101’ – 2 cycles

If the burst bits (ROMCR[4:3]) are programmed to a value other than ‘00’, then the total worst-case num-

ber of cycles is one multiplied by the non-sequential number above, plus three multiplied by the burst num-

ber from the following:

‘01’ – 4 cycles

For all:

‘10’ – 3 cycles

Multiply by 2 if 16-bit mode set

‘11’ – 2 cycles

Multiply by 2 if half-speed bit set

At this point calculate the number of cycles required for a worst-case DRAM access. This can be the only

limiting factor when 16-bit-wide DRAM is used, and in this case the delay is:

9 + (2 × 7) = 23 cycles

Equation 20-1

As described above, the worst-case delay for four sequential internal register programming cycles is 16

cycles. Therefore, the worst-case delay is caused by internal register access cycles, ROM or DRAM

according to the worst-case results of the above calculations.

DMA can continue over the top of I/O accesses, so these do not feature in the options for worst case delay.

So for a system that is limited by internal register access cycles, the worst case latency is:

3.5 + 2 + 16 + 5.5 = 27 MEMCLK cycles

Equation 20-2

So if MEMCLK is running at 32 MHz, the total worst-case DMA latency is 0.84 µs.

June 1997

ADVANCE DATA BOOK v2.0

BUS INTERFACE

189

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