CL-PS7500FE データシートの表示（PDF） - Cirrus Logic
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CL-PS7500FE Datasheet PDF : 251 Pages
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CL-PS7500FE
System-on-a-Chip for Internet Appliance
22.7 I/O Subsystems
Table 22-6. Simple 8-MHz I/O Timing
Symbol Parameter
tclk8l
tclk8h
tclk2l
tclk2h
tcsl_sio
tcsh_sio
tbd1 a
tbd1s b
tbd2c, d
tbd2c, e
tbdh
tbds
tiornwh
tiornwl
tniorl
tniorh
tniowl
tniowh
tadd1 f
tadd1s g
tadd2d, h
tadd2e, h
I_OCLK rising to CLK8 falling
I_OCLK rising to CLK8 rising
I_OCLK rising to CLK2 falling
I_OCLK rising to CLK2 rising
I_OCLK rising to nSIOCS1/nSIOCS2 falling
I_OCLK rising to nSIOCS1/nSIOCS2 rising
I_OCLK rising to BD write data valid
I_OCLK rising to BD write data valid (SYNC cycles)
I_OCLK rising to BD write data valid
I_OCLK rising to BD write data valid
DATA hold from I_OCLK rising
DATA setup to I_OCLK rising
I_OCLK falling to IORNW rising
I_OCLK rising to IORNW falling
I_OCLK rising to nIOR falling
I_OCLK rising to nIOR rising
I_OCLK rising to nIOW falling
I_OCLK rising to nIOW rising
LA[28:0] changing after I_CLK rising before start
LA[28:0] changing after I_OCLK rising before start (SYNC cycle)
LA[28:0] changing after I_OCLK rising after end
LA[28:0] changing after I_OCLK rising after end
a Synchronization penalty is between 0 and 3 I_OCLK cycles.
b Synchronization penalty is between 0 and 15 I_OCLK cycles.
c Delay includes 4 MEMCLK cycles.
d Timings refer to the case where ASTCR bit = 0.
e Timings refer to the worst case where ASTCR bit = 1 (see Appendix C ).
f Synchronization penalty is between 0 and 4 I_OCLK cycles.
g Synchronization penalty is between 0 and 16 I_OCLK cycles.
h Delay includes 2 MEMCLK cycles.
40 MHz
MIN MAX
14
14
16
16
19
20
0
102
0
476
133 152
149 168
10
0
13
16
16
16
17
16
0
143
0
518
74
89
90 105
56 MHz
Units
MIN MAX
14
ns
14
ns
16
ns
16
ns
19
ns
20
ns
0
102
ns
0
476
ns
133 152
ns
149 168
ns
10
ns
0
13
ns
16
ns
16
ns
16
ns
17
ns
16
ns
0
143
ns
0
518
ns
74
89
ns
90
105
ns
June 1997
ADVANCE DATA BOOK v2.0
ELECTRICAL SPECIFICATIONS
209
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