CL-PS7500FE データシートの表示（PDF） - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

6.7 MMU Faults and CPU Aborts

The MMU generates four types of faults:

q Alignment

q Translation

q Domain

q Permission

The access control mechanisms of the MMU detect the conditions that produce these faults. If a fault is

detected as the result of a memory access, the MMU aborts the access and signal the fault condition to

the CPU. The MMU is also capable of retaining status and address information about the abort. The CPU

recognizes two types of abort, data and prefetch, and these are treated differently by the MMU.

If the MMU detects an access violation, it detects it before the external memory access occurs, and inhibit

the access.

6.8 Fault Address and Fault Status Registers (FAR, FSR)

Aborts resulting from data accesses (data aborts) are acted upon by the CPU immediately, and the MMU

places an encoded 4-bit value FS[3:0], along with the 4-bit encoded Domain number, in the FSR. In addi-

tion, the virtual processor address that caused the data abort is latched into the FAR. If an access viola-

tion simultaneously generates more than one source of abort, they are encoded in the priority given in

Table 6-4.

On the other hand, CPU instructions are prefetched so a prefetch abort simply flags the instruction as it

enters the instruction pipeline. Only when (and if) the instruction is executed does it cause an abort; an

abort is not acted upon if the instruction is not used (that is, it is branched around). Because instruction

prefetch aborts may or may not be acted upon, the MMU status information is not preserved for the result-

ing CPU abort; for a prefetch abort, the MMU does not update the FSR or FAR.

The following sections describe the various access permissions and controls supported by the MMU and

detail how these are interpreted to generate faults.

In Table 6-4 X indicates a don’t care state and can read as ‘0’ or ‘1’.

NOTE: Any abort masked by the priority encoding can be regenerated by fixing the primary abort and restarting the

instruction. In fact, this register contains bits 8:5 of the Level One entry, which are undefined, but would

encode the domain in a valid entry.

Table 6-4. Priority Encoding of Fault Status Register

Priority

Highest

Lowest

Source

Alignment

Translation (Section)

Translation (Page)

Domain (Section)

Domain (Page)

Permission (Section)

Permission (Page)

FS[3:0]

00x1

0101

0111

1001

1011

1101

1111

Domain [3:0]

X

Note 2

Valid

Valid

Valid

Valid

Valid

FAR

Valid

Valid

Valid

Valid

Valid

Valid

Valid

June 1997

ADVANCE DATA BOOK v2.0

47

ARM PROCESSOR MMU

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