LH28F800BGE-BL12 データシートの表示（PDF） - Sharp Electronics
部品番号
コンポーネント説明
メーカー
LH28F800BGE-BL12 Datasheet PDF : 43 Pages
| |||
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS (contd.) (NOTE 1)
• VCC = 5.0±0.25 V, 5.0±0.5 V, TA = 0 to +70˚C or –40 to +85˚C
VERSIONS
(NOTE 5)
VCC±0.25 V LH28F800BG-L85
LH28F800BGH-L85
VCC±0.5 V
(NOTE 6)
(NOTE 6)
UNIT
LH28F800BG-L85 LH28F800BG-L12
LH28F800BGH-L85 LH28F800BGH-L12
SYMBOL
PARAMETER
NOTE MIN. MAX. MIN. MAX. MIN. MAX.
tAVAV Write Cycle Time
85
90
120
ns
RP# High Recovery to WE#
tPHWL
2
1
1
1
µs
Going Low
tELWL CE# Setup to WE# Going Low
10
10
10
ns
tWLWH WE# Pulse Width
40
40
40
ns
tPHHWH RP# VHH Setup to WE# Going High 2
100
100
100
ns
tSHWH WP# VIH Setup to WE# Going High 2
100
100
100
ns
tVPWH VPP Setup to WE# Going High 2
100
100
100
ns
tAVWH Address Setup to WE# Going High 3
40
40
40
ns
tDVWH Data Setup to WE# Going High 3
40
40
40
ns
tWHDX Data Hold from WE# High
5
5
5
ns
tWHAX Address Hold from WE# High
5
5
5
ns
tWHEH CE# Hold from WE# High
10
10
10
ns
tWHWL WE# Pulse Width High
30
30
30
ns
tWHRL WE# High to RY/BY# Going Low
90
90
90 ns
tWHGL Write Recovery before Read
0
0
0
ns
VPP Hold from Valid SRD,
tQVVL
2, 4
0
0
0
ns
RY/BY# High
RP# VHH Hold from Valid SRD,
tQVPH
2, 4
0
0
0
ns
RY/BY# High
WP# VIH Hold from Valid SRD,
tQVSL
2, 4
0
0
0
ns
RY/BY# High
NOTES :
1. Read timing characteristics during block erase and word
write operations are the same as during read-only
operations. Refer to Section 6.2.4 "AC CHARAC-
TERISTICS" for read-only operations.
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid AIN and DIN for block erase or
word write.
4. VPP should be held at VPPH1/2/3 (and if necessary RP#
should be held at VHH) until determination of block erase
or word write success (SR.1/3/4/5 = 0 : on Boot Blocks,
SR.3/4/5 = 0 : on Parameter Blocks and Main Blocks).
5. See Fig. 8 "Transient Input/Output Reference
Waveform" and Fig. 10 "Transient Equivalent Testing
Load Circuit" (High Seed Configuration) for testing
characteristics.
6. See Fig. 9 "Transient Input/Output Reference
Waveform" and Fig. 10 "Transient Equivalent Testing
Load Circuit" (Standard Configuration) for testing
characteristics.
- 32 -
Share Link: 