PIC16LF1826-I/SS データシートの表示（PDF） - Microchip Technology
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PIC16LF1826-I/SS
Microchip Technology
PIC16LF1826-I/SS Datasheet PDF : 406 Pages
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TABLE 3-3: PIC16F/LF1826/27 MEMORY MAP, BANKS 0-7
BANK0
BANK1
BANK2
BANK3
000h
001h
002h
003h
004h
005h
006h
007h
008h
009h
00Ah
00Bh
00Ch
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
PORTA
080h
081h
082h
083h
084h
085h
086h
087h
088h
089h
08Ah
08Bh
08Ch
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
TRISA
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
LATA
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
ANSELA
00Dh
00Eh
00Fh
010h
PORTB
—
—
—
08Dh
08Eh
08Fh
090h
TRISB
—
—
—
10Dh
10Eh
10Fh
110h
LATB
—
—
—
18Dh
18Eh
18Fh
190h
ANSELB
—
—
—
011h
PIR1
091h
PIE1
111h CM1CON0 191h
EEADRL
012h
013h
014h
015h
016h
017h
PIR2
PIR3(1)
PIR4(1)
TMR0
TMR1L
TMR1H
092h
093h
094h
095h
096h
097h
PIE2
PIE3(1)
PIE4(1)
OPTION
PCON
WDTCON
112h
113h
114h
115h
116h
117h
CM1CON1
CM2CON0
CM2CON1
CMOUT
BORCON
FVRCON
192h
193h
194h
195h
196h
197h
EEADRH
EEDATL
EEDATH
EECON1
EECON2
—
018h
T1CON
098h OSCTUNE 118h DACCON0 198h
—
019h
T1GCON
099h
OSCCON
119h DACCON1 199h
RCREG
01Ah
TMR2
09Ah OSCSTAT 11Ah SRCON0 19Ah
TXREG
01Bh
01Ch
PR2
T2CON
09Bh
09Ch
ADRESL
ADRESH
11Bh
11Ch
SRCON1
—
19Bh
19Ch
SPBRGL
SPBRGH
01Dh
—
09Dh ADCON0 11Dh APFCON0 19Dh
RCSTA
01Eh CPSCON0 09Eh ADCON1 11Eh APFCON1 19Eh
TXSTA
01Fh CPSCON1 09Fh
—
11Fh
—
19Fh BAUDCON
020h
0A0h
120h
1A0h
06Fh
070h
07Fh
General
Purpose
Register
96 Bytes
0EFh
0F0h
0FFh
General
Purpose
Register
80 Bytes
Accesses
70h – 7Fh
16Fh
170h
17Fh
General
Purpose
Register
80 Bytes
Accesses
70h – 7Fh
1EFh
1F0h
1FFh
General
Purpose
Register
80 Bytes(1)
Accesses
70h – 7Fh
Legend:
Note 1:
= Unimplemented data memory locations, read as ‘0’
Available only on PIC16F/LF1827.
200h
201h
202h
203h
204h
205h
206h
207h
208h
209h
20Ah
20Bh
20Ch
20Dh
20Eh
20Fh
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
21Fh
220h
26Fh
270h
27Fh
BANK4
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
WPUA
WPUB
—
—
—
SSP1BUF
SSP1ADD
SSP1MASK
SSP1STAT
SSP1CON
SSP1CON2
SSP1CON3
—
SSP2BUF(1)
SSP2ADD(1)
SSP2MASK(1)
SSP2STAT(1)
SSP2CON(1)
SSP2CON2(1)
SSP2CON3(1)
General
Purpose
Register
48 Bytes(1)
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
280h
281h
282h
283h
284h
285h
286h
287h
288h
289h
28Ah
28Bh
28Ch
28Dh
28Eh
28Fh
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
29Fh
2A0h
2EFh
2F0h
2FFh
BANK5
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
—
—
—
—
CCPR1L
CCPR1H
CCP1CON
PWM1CON
CCP1AS
PSTR1CON
—
CCPR2L(1)
CCPR2H(1)
CCP2CON(1)
PWM2CON(1)
CCP2AS(1)
PSTR2CON(1)
CCPTMRS(1)
—
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
300h
301h
302h
303h
304h
305h
306h
307h
308h
309h
30Ah
30Bh
30Ch
30Dh
30Eh
30Fh
310h
311h
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
31Fh
320h
36Fh
370h
37Fh
BANK6
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
—
—
—
—
CCPR3L(1)
CCPR3H(1)
CCP3CON(1)
—
—
—
—
CCPR4L(1)
CCPR4H(1)
CCP4CON(1)
—
—
—
—
—
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
380h
381h
382h
383h
384h
385h
386h
387h
388h
389h
38Ah
38Bh
38Ch
38Dh
38Eh
38Fh
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
39Fh
3A0h
3EFh
3F0h
3FFh
BANK7
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
—
—
—
—
—
—
—
IOCBP
IOCBN
IOCBF
—
—
—
CLKRCON
—
MDCON
MDSRC
MDCARL
MDCARH
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
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