Table 35. IPH0 Register
IPH0 - Interrupt Priority High Register (B7h)
7
6
5
4
-
PPCH
PT2H
PSH
3
PT1H
2
PX1H
1
PT0H
Bit
Number
7
6
Bit
Mnemonic Description
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
PPCH
PCA interrupt priority high bit.
PPCH PPCL Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
Timer 2 overflow interrupt priority high bit
PT2H PT2L Priority Level
5
PT2H
0
0
0
1
Lowest
1
0
1
1
Highest
Serial port priority high bit
PSH PSL Priority Level
4
PSH
0
0
0
Lowest
1
1
0
1
1
Highest
Timer 1 overflow interrupt priority high bit
PT1H PT1L Priority Level
3
PT1H
0
0
0
1
Lowest
1
0
1
1
Highest
External interrupt 1 priority high bit
PX1H PX1L Priority Level
2
PX1H
0
0
0
1
Lowest
1
0
1
1
Highest
Timer 0 overflow interrupt priority high bit
PT0H PT0L Priority Level
1
PT0H
0
0
0
1
Lowest
1
0
1
1
Highest
External interrupt 0 priority high bit
PX0H PX0L Priority Level
0
PX0H
0
0
0
1
Lowest
1
0
1
1
Highest
Reset Value = X000 0000b
Not bit addressable
0
PX0H
50 AT80C51RD2/AT83C51Rx2
4113B–8051–03/05