AT89C51RC2-3CSCM(2003) データシートの表示（PDF） - Atmel Corporation
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AT89C51RC2-3CSCM Datasheet PDF : 125 Pages
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AT89C51RB2/RC2
Bit Number
Bit Mnemonic
2
SPR1
1
SPR0
Reset Value = 0001 0100b
Not bit addressable
Description
SPR2
0
0
0
0
1
1
1
1
SPR1
0
0
1
1
0
0
1
1
SPR0 Serial Peripheral Rate
0
Invalid
1
FCLK PERIPH /4
0
FCLK PERIPH /8
1
FCLK PERIPH /16
0
FCLK PERIPH /32
1
FCLK PERIPH /64
0
FCLK PERIPH /128
1
Invalid
Serial Peripheral Status Register
(SPSTA)
The Serial Peripheral Status Register contains flags to signal the following conditions:
• Data transfer complete
• Write collision
• Inconsistent logic level on SS pin (mode fault error)
Table 57 describes the SPSTA register and explains the use of every bit in the register.
Table 57. SPSTA Register
SPSTA - Serial Peripheral Status and Control register (0C4H)
7
6
5
4
3
2
1
0
SPIF
WCOL
SSERR
MODF
-
-
-
-
Bit
Bit
Number Mnemonic Description
Serial Peripheral Data Transfer Flag
7
SPIF
Cleared by hardware to indicate data transfer is in progress or has been
approved by a clearing sequence.
Set by hardware to indicate that the data transfer has been completed.
Write Collision Flag
6
WCOL
Cleared by hardware to indicate that no collision has occurred or has been
approved by a clearing sequence.
Set by hardware to indicate that a collision has been detected.
Synchronous Serial Slave Error Flag
5
SSERR Set by hardware when SS is deasserted before the end of a received data.
Cleared by disabling the SPI (clearing SPEN bit in SPCON).
Mode Fault
4
MODF
Cleared by hardware to indicate that the SS pin is at appropriate logic level, or
has been approved by a clearing sequence.
Set by hardware to indicate that the SS pin is at inappropriate logic level.
Reserved
3
-
The value read from this bit is indeterminate. Do not set this bit
Reserved
2
-
The value read from this bit is indeterminate. Do not set this bit.
73
4180B–8051–04/03
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