CS5368(2005) データシートの表示（PDF） - Cirrus Logic

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CS5368
(Rev.:2005)

114 dB, 192 kHz, 8-Channel A/D Converter

Cirrus Logic 

4. APPLICATIONS

CS5368

4.1 Power

For convenient interfacing to external devices, there are five independent power pins for the CS5368. VD

powers the digital core. VA powers the analog core. VLS powers the Serial Audio Interface. VLC powers

the control logic. VX powers the crystal oscillator. The power pins may have any supported voltage range

of the specified voltages supplied simultaneously.

To meet full performance specifications, the CS5368 requires normal low noise board layout. The “Typical

Connection Diagram” on page 23 shows the recommended power arrangements, with VA connected to a

clean supply. VD, which powers the digital filter, may be run from the system logic supply, or it may be pow-

ered from the analog supply via a single-pole decoupling filter.

Decoupling capacitors should be placed as near to the ADC as possible, with the lower value high frequency

capacitors being placed nearest to the device leads. Clocks should be kept away from the FILT+ and VQ

pins in order to avoid unwanted coupling into the device. The FILT+ and VQ decoupling capacitors must be

positioned to minimize the electrical path to ground.

The CDB5368 evaluation board demonstrates an optimum layout for the device.

4.2 Clocking

The device supports clocking through the use of either an on-board crystal oscillator driver or an externally

supplied clock. When using the on-board crystal driver, the topology shown in Figure 8. "Crystal Oscillator

Topology" must be used. The crystal oscillator manufacturer supplies recommended capacitor values.

XTI 21

XTO 22

Figure 8. Crystal Oscillator Topology

When using the on-board crystal oscillator driver, the XTI pin is the input for the Master clock (MCLK) to the

device. The XTO pin must not be used to drive anything other than the oscillator tank circuitry. Instead, a

buffered copy of XTI is available on the MCLK pin, which is level controlled by VLS and may be used to

synchronize other parts to the device.

If an external clock is used, the XTI and XTO pins must be grounded, and the MCLK pin becomes an input

for the system Master clock.

The CS5368 provides on board master clock dividers that precede all other internal clocking. The available

dividers are divide by 1, 1.5, 2, 3, 4.

DS624A1

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