CS5368(2005) データシートの表示（PDF） - Cirrus Logic
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CS5368 Datasheet PDF : 39 Pages
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CS5368
4.6.9 Master and Slave Clock Frequencies
Tables 4 through 9 show the clock speeds for sample rates of 48 kHz, 96 kHz and 192 kHz. In Master
Mode, the device outputs the frequencies shown. In Slave Mode, the SCLK/LRCK ratio can be set ac-
cording to design preference. However, device performance is guaranteed only when using the ratios
shown in the tables
.
Control Port Mode only
LJ/I²S MASTER OR SLAVE
MCLK Divider
MCLK (MHz)
÷4
49.152
÷3
36.864
SSM
÷2
24.576
SCLK(MHz)
3.072
3.072
3.072
MCLK/LRCK Ratio
1024
768
512
SCLK/LRCK Ratio
64
64
64
Table 4. Frequencies for 48 kHz Sample Rate using LJ/I²S
÷1.5
18.384
3.072
384
64
LJ/I²S MASTER OR SLAVE
MCLK Divider
MCLK (MHz)
SCLK(MHz)
MCLK/LRCK Ratio
SCLK/LRCK Ratio
÷4
49.152
6.144
512
64
÷3
36.864
6.144
384
64
DSM
÷2
24.567
6.144
256
64
Table 5. Frequencies for 96 kHz Sample Rate using LJ/I²S
÷1.5
18.384
6.144
192
64
LJ/I²S MASTER OR SLAVE
MCLK Divider
MCLK (MHz)
SCLK (MHz)
MCLK/LRCK Ratio
SCLK/LRCK Ratio
÷4
49.152
12.288
256
64
÷3
36.864
12.288
192
64
QSM
÷2
24
12.288
128
64
Table 6. Frequencies for 192 kHz Sample Rate using LJ/I²S
÷1.5
18.384
12.288
96
64
TDM MASTER OR SLAVE
MCLK Divider
MCLK (MHz)
SCLK (MHz)
MCLK/FS Ratio
SCLK/FS Ratio
÷4
49.152
12.288
1024
256
÷3
36.864
12.288
768
256
SSM
÷2
24.567
12.288
512
256
Table 7. Frequencies for 48 kHz Sample Rate using TDM
÷1.5
18.384
12.288
384
256
÷1
12.288
3.072
256
64
÷1
12.288
6.144
128
64
÷1
12.288
12.288
64
64
÷1
12.288
12.288
256
256
DS624A1
29
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