CS5368(2005) データシートの表示（PDF） - Cirrus Logic
部品番号
コンポーネント説明
メーカー
CS5368 Datasheet PDF : 39 Pages
| |||
5.5 03h (OVFM) Overflow Mask Register
R/W
R/W
7
OVFM8
6
OVFM7
5
OVFM6
4
OVFM5
3
OVFM4
2
OVFM3
CS5368
1
OVFM2
0
OVFM1
Default: 0xFF, all overflow interrupts enabled.
The Overflow Mask Register is used to allow or prevent individual channel overflow events from
creating activity on the OVFL pin. When a particular bit is set low in the Mask register, the
corresponding overflow bit in the Overflow Status register is prevented from causing any activity
on the OVFL pin.
5.6 04h (HPF) High-Pass Filter Register
R/W
7
6
5
4
R/W
HPF8
HPF7
HPF6
HPF5
3
HPF4
2
HPF3
1
HPF2
0
HPF1
Default: 0x00, all high-pass filters enabled.
The High-Pass Filter Register is used to enable or disable a high-pass filter that exists for each
channel. These filters are used to perform DC offset calibration, a procedure that is detailed in
“DC Offset Control” on page 26.
5.7 05h Reserved
R/W
7
6
5
4
3
2
1
0
Reserved
-
-
-
-
-
-
-
-
5.8 06h (PDN) Power Down Register
R/W
R/W
7
6
RESERVED
5
4
PDN-BG PDN-OSC
3
PDN87
2
PDN65
1
PDN43
0
PDN21
Default: 0x00 - everything powered up
The Power Down Register is used as needed to reduce the chip’s power consumption.
Bit[7] RESERVED
Bit[6] RESERVED
Bit[5] PDN-BG When set, this bit powers-down the bandgap reference.
Bit[4] PDN-OSC controls power to the internal oscillator core. When asserted, the internal oscil-
lator core is shut down, and no clock is supplied to the chip. If the chip is running off an externally
supplied clock at the MCLK pin, it is also prevented from clocking the device internally.
Bit[3:0] PDN When any bit is set, all clocks going to a channel pair are turned off, and the serial
data outputs are forced to all zeroes.
DS624A1
37
Share Link: 