M25P10-AVMP6GX データシートの表示（PDF） - Numonyx -> Micron

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M25P10-AVMP6GX

1 Mbit, serial Flash memory, 50 MHz SPI bus interface

Numonyx -> Micron 

Revision history

M25P10-A

Table 25. Document revision history (continued)

Date

Revision

Changes

05-Jun-2006

tRES1 and tRES2 parameter timings changed for devices produced with the

“X” process technology in Table 18 and Table 19.

7

SO8 narrow package specifications updated (see Figure 26 and

Table 21).

06-Jul-2007

23-Aug-2007

Changed the minimum value for supply voltage.

Added TLEAD and changed maximum value for VIO in Table 9: Absolute

maximum ratings.

Updated Section 3: SPI modes and modified Figure 3: Bus master and

8

memory devices on the SPI bus.

Note 1 to Table 13: Capacitance changed.

Note 2 below Table 16: Instruction times (device grade 6) added.

Changed test condition for ICC3 in Table 14 and fR in Table 20.

Removed “low voltage” from the title. Small text changes.

Typical values for Sector Erase and Bulk Erase modified.

UFDFPN8 package (MLP8) added.

9

Added the reference to a new process technology (code “Y”).

Added notes below Table 10: Operating conditions, Table 15: DC

characteristics (device grade 3), and Table 17: Instruction times (device

grade 3).

/Y process added to Table 24: Ordering information scheme.

18-Oct-2007

Code of the UFDFPN8 package modified.

10

Small text changes.

10-Dec-2007 11 Applied Numonyx branding.

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