M50FLW040AN5T データシートの表示（PDF） - STMicroelectronics

部品番号

コンポーネント説明

メーカー

M50FLW040AN5T

4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory

STMicroelectronics 

M50FLW040A, M50FLW040B

Table 7. FWH Bus Write Field Definitions

Clock

Cycle

Number

Clock

Cycle

Count

Field

FWH0- Memory

FWH3 I/O

Description

1

1

START 1110b

I

On the rising edge of CLK with FWH4 Low, the contents of

FWH0-FWH3 indicate the start of a FWH Write Cycle.

Indicates which FWH Flash Memory is selected. The value on

2

1

IDSEL XXXX

I

FWH0-FWH3 is compared to the IDSEL strapping on the FWH

Flash Memory pins to select which FWH Flash Memory is being

addressed.

A 28-bit address is transferred, with the most significant nibble

first. Address lines A19-21 and A23-27 are treated as Don’t

3-9

7

ADDR XXXX

I

Care during a normal memory array access, with A22=1, but are

taken into account for a register access, with A22=0. (See Table

15.)

10

1

MSIZE XXXX

I

0000(Single Byte Transfer) 0001 (Double Byte Transfer) 0010b

(Quadruple Byte Transfer).

11-18 M=2/4/8 DATA XXXX

Data transfer is two cycles, starting with the least significant

nibble. (The first pair of nibbles is that at the address with A1-

I

A0 set to 00, the second pair with A1-A0 set to 01, the third

pair with A1-A0 set to 10, and the fourth pair with A1-A0 set

to 11. In Double Byte Program the first pair of nibbles is that at

the address with A0 set to 0, the second pair with A0 set to 1)

previous

+1

1

TAR 1111b

I

The host drives FWH0-FWH3 to 1111b to indicate a turnaround

cycle.

previous

+1

1

TAR

1111b

(float)

O

The FWH Flash Memory takes control of FWH0-FWH3 during

this cycle.

previous

+1

1

SYNC 0000b

O

The FWH Flash Memory drives FWH0-FWH3 to 0000b,

indicating it has received data or a command.

previous

+1

1

TAR 1111b

O

The FWH Flash Memory drives FWH0-FWH3 to 1111b,

indicating a turnaround cycle.

previous

+1

1

TAR

1111b

(float)

N/A

The FWH Flash Memory floats its outputs and the host takes

control of FWH0-FWH3.

Figure 8. FWH Bus Write Waveforms

CLK

FWH4

FWH0-FWH3

Number of

clock cycles

START

1

IDSEL

1

ADDR

7

MSIZE

1

DATA

M

TAR

2

SYNC

1

TAR

2

AI08434B

15/52

Share Link: