JS48F4400PCZ00 データシートの表示（PDF） - Numonyx -> Micron

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JS48F4400PCZ00

Numonyx™ Wireless Flash Memory (W18)

Numonyx -> Micron 

Numonyx™ Wireless Flash Memory (W18)

Figure 9: Single Synchronous Read-Array Operation Waveform

R13

R12

Notes:

1.

Section 14.2, “First Access Latency Count (RCR[13:11])” on page 79 describes how to insert clock

cycles during the initial access.

2.

WAIT (shown asserted; RCR[10]=0) can be configured to assert either during, or one data cycle before, valid data.

3.

This waveform illustrates the case in which an x-word burst is initiated to the main array and it is terminated by a CE# de-

assertion after the first word in the burst. If this access had been done to Status, ID, or Query reads, the asserted (low)

WAIT signal would have remained asserted (low) as long as CE# is asserted (low).

Datasheet

32

November 2007

Order Number: 290701-18

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