Numonyx™ Wireless Flash Memory (W18)
Figure 11: WAIT Functionality for EOWL (End-of-Word Line) Condition Waveform
R12
Notes:
1.
Section 14.2, “First Access Latency Count (RCR[13:11])” on page 79 describes how to insert clock
cycles during the initial access.
2.
WAIT (shown asserted; RCR[10]=0) can be configured to assert either during, or one data cycle before, valid data
(assumed wait delay of two clocks, for example).
Datasheet
34
November 2007
Order Number: 290701-18