PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 23-8: PARALLEL SLAVE PORT TIMING (PIC16C67)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
64
Note: Refer to Figure 23-1 for load conditions
62
63
TABLE 23-7: PARALLEL SLAVE PORT REQUIREMENTS (PIC16C67)
Parameter
No.
Sym Characteristic
62*
TdtV2wrH Data in valid before WR↑ or CS↑ (setup time)
Min Typ† Max Units Conditions
20 —
—
ns
25 —
—
ns
Extended
Range Only
63*
TwrH2dtI WR↑ or CS↑ to data–in invalid (hold PIC16C67
time)
PIC16LC67
20 —
—
ns
35 —
—
ns
64
TrdL2dtV RD↓ and CS↓ to data–out valid
—
—
80
ns
—
—
90
ns
Extended
Range Only
65*
TrdH2dtI RD↑ or CS↑ to data–out invalid
10 —
30
ns
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30234D-page 274
© 1997 Microchip Technology Inc.